Embodiments of the present disclosure provides an array substrate and a manufacturing method thereof, a display panel. The array substrate includes: a base; a pixel electrode and a thin film transistor disposed on the base; a passivation layer covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole that simultaneously exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor; a connection electrode disposed on the passivation layer and at the transferring through hole, the connection electrode connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole.

The present disclosure provides a photodiode, a display substrate, and manufacturing methods thereof, and a display device. The method for manufacturing the photodiode includes: forming a semiconductor material layer on a base substrate in a non-display region of a display substrate, the semiconductor material layer including a first contact area, a second contact area, and a semiconductor area sandwiched therebetween; processing the first contact area of the semiconductor material layer to form a first contact electrode; processing portions of the semiconductor material layer and the second contact area away from the base substrate in the semiconductor area, to form a first semiconductor layer and a second semiconductor layer stacked, the second semiconductor layer being located on a side of the first semiconductor layer away from the base substrate; and processing the second semiconductor layer in the second contact area to form a second contact electrode.

A display panel, a preparation method thereof, and a display device are disclosed. The display panel includes: a plurality of pixel units arranged in an array; a plurality of first signal lines extending in a first direction and arranged in a second direction; and a plurality of first connecting electrodes arranged in the second direction; where the first direction intersects with the second direction. The plurality of pixel units form m pixel rows arranged in sequence along the first direction and each extending along the second direction, where m is an integer greater than 1; and a projection of at least one pixel unit in an m-th pixel row on a plane perpendicular to the second direction and projections of the first connecting electrodes on the plane perpendicular to the second direction have an overlapped area.

Provided is a display substrate. The display substrate includes: a base substrate including a display region and a non-display region surrounding the display region; a gate drive circuit disposed in the non-display region; a plurality of first signal lines disposed in the peripheral region and connected to the gate drive circuit; and a plurality of second signal lines disposed in the non-display region and connected to the gate drive circuit; wherein each of the first signal line and the second signal line is configured to supply a signal to the gate drive circuit, and a frequency of the signal supplied by the first signal line is lower than a frequency of the signal supplied by the second signal line.

A display panel, a fabrication method thereof, and a display device are provided. The display panel is divided into a display area, a line switching area, and a bending area in a horizontal direction and includes a substrate, a barrier layer, a buffer layer, an active layer, a first gate insulating layer, a first metal layer, and a second gate insulating layer sequentially formed from bottom to top. The display panel further includes a first through hole, a second metal layer, a first organic layer, a second metal layer, an interlayer insulating layer, and a third metal layer, wherein a portion of the third metal layer penetrates the interlayer insulating layer and is electrically connected to the second metal layer.

A display backplane includes a substrate, a thin film transistor over the substrate, and a pixel capacitor assembly over a side of the thin film transistor away from the substrate, and an orthographic projection of the pixel capacitor assembly on the substrate covers at least one portion of an orthographic projection of the thin film transistor on the substrate. The pixel capacitor assembly includes a first electrode, a passivation layer, and a second electrode, sequentially over a side of the thin film transistor away from the substrate, and an orthographic projection of the first electrode on the substrate is overlapped with the orthographic projection of the thin film transistor on the substrate. A display panel including the display backplane can further include an OLED component, arranged over a side of the pixel capacitor assembly away from the substrate.

A capacitor, an array substrate and a method for manufacturing the same, and a display panel are provided. The capacitor includes a main body including a first pole plate and a second pole plate disposed opposite to each other, and the capacitor further includes at least one auxiliary body. Any one of the at least one auxiliary body includes a third pole plate and a fourth pole plate disposed opposite to each other, and neither the third pole plate nor the fourth pole plate extends in a plane where the first pole plate is located or a plane where the second pole plate is located. The main body is connected in parallel with the at least one auxiliary body. The array substrate includes a transistor and the capacitor provided by the present disclosure, and the transistor is electrically connected to the capacitor.

A method of fabricating an array substrate is provided. The array substrate includes a display region and a non-display region. The array substrate further includes a substrate, a first transparent layer disposed on the substrate corresponding to the display region, an interlayer insulating layer disposed on the substrate, and a second transparent layer disposed on the interlayer insulating layer.

A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.

A display device includes a first electrode is disposed on a substrate, a pixel defining layer disposed on the substrate in a non-emission area and defining an emission area, a reflection pattern protrudes upward from the first electrode in the emission area and forming a concave part on the first electrode, a light emitting element disposed in the concave part and electrically connected to the first electrode, and a second electrode disposed on the light emitting element and electrically connected to the light emitting element. The reflection pattern does not overlap the pixel defining layer in a plan view.