Methods for integrating an image sensor and a light emitting diode (LED) leverage conformal depositions to achieve a single-sided, same height arrangement of contacts. In some embodiments, the method includes forming a plurality of cavities on a substrate where the plurality of cavities have a cavity profile and are configured to accept an emitter pixel structure or a sensor pixel structure, forming an emitter pixel structure in a cavity on the substrate where the emitter pixel structure is configured to have a plurality of exposed direct emitter contact areas on a same side and at a same height, and forming at least one sensor pixel structure in a cavity on the substrate where the sensor pixel structure is configured to have a plurality of exposed direct sensor contact areas on a same side and at a same height.

Described herein are techniques that improve the collection and readout of charge carriers in an integrated circuit. Some aspects of the present disclosure relate to integrated circuits having pixels with a plurality of charge storage regions. Some aspects of the present disclosure relate to integrated circuits configured to substantially simultaneously collect and read out charge carriers, at least in part. Some aspects of the present disclosure relate to integrated circuits having a plurality of pixels configured to transfer charge carriers between charge storage regions within each pixel substantially at the same time. Some aspects of the present disclosure relate to integrated circuits having three or more sequentially coupled charge storage regions. Some aspects of the present disclosure relate to integrated circuits capable of increased charge transfer rates. Some aspects of the present disclosure relate to techniques for manufacturing and operating integrated circuits according to the other techniques described herein.

A detection element, a manufacturing method thereof and a flat panel detector are disclosed. The detection element includes: a base substrate; a first electrode on the base substrate; a photoelectric conversion layer; a transparent electrode and a second electrode electrically connected with the transparent electrode on a side of the photoelectric conversion layer away from the first electrode. An orthographic projection of the photoelectric conversion layer on the base substrate completely falls within an orthographic projection of the first electrode on the base substrate, in a plane parallel to the base substrate, the transparent electrode is located at a middle portion of the photoelectric conversion, an orthographic projection of a portion of the photoelectric conversion layer not covered by the transparent electrode on the base substrate at least partially falls within an orthographic projection of the second electrode on the base substrate.

The present disclosure relates a method of forming an integrated chip structure. The method includes etching a base substrate to form a recess defined by one or more interior surfaces of the base substrate. A doped epitaxial layer is formed along the one or more interior surfaces of the base substrate, and an epitaxial material is formed on horizontally and vertically extending surfaces of the doped epitaxial layer. A first doped photodiode region is formed within the epitaxial material and a second doped photodiode region is formed within the epitaxial material. The first doped photodiode region has a first doping type and the second doped photodiode region has a second doping type.

A chip package includes a sensing element, a dam layer, and a light transmissive cover. A surface of the sensing element has a sensing area and a conductive pad. The conductive pad is adjacent to an edge of the surface of the sensing element. The dam layer is located on the surface of the sensing element and surrounds the sensing area. The dam layer has a main portion and plural mark portions. The mark portions are respectively located in plural corners of the main portion, located in a sidewall of the main portion, respectively located on plural corners of the sensing element, respectively located on plural inner edges of the main portion, or respectively located on plural outer edges of the main portion. The light transmissive cover is located on the dam layer.

The present disclosure provides a chip packaging structure and a chip packaging method, relating to the technical field of chip packaging. In the above, the chip packaging structure includes: a substrate, wherein a light-transmitting hole penetrating through upper and lower surfaces thereof is provided on the substrate, and openings communicated with the light-transmitting hole are formed on two opposite sidewall surfaces of the substrate, respectively; light-transmitting glass, wherein two opposite sides of the light-transmitting glass are inserted into the two openings, respectively, and shield the light-transmitting hole; a chip, provided on the upper surface of the substrate, wherein a photosensitive area of the chip faces the light-transmitting glass; and a packaging layer, provided on the chip and the upper surface of the substrate so as to package the chip on the substrate.

The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

A semiconductor-based imaging device and method of manufacture. A direct bond hybridization (DBH) structure is formed on a top surface of a read out integrated circuit (ROIC). A silicon-based detector is bonded to the ROIC via the DBH structure. A non-silicon-based detector is bonded to the DBH structure located on the top of the ROIC using indium-based hybridization.

Provided is an image sensor including a light sensing element, a planarization layer disposed on the light sensing element, a color filter array layer disposed on the planarization layer, the color filter array layer including color filters, and a microlens disposed on the color filter array layer, wherein the color filters include a green filter, a blue filter and a red filter, and wherein a refractive index of the green filter is greater than 1.7 for a green light wavelength range of 500 nm to 570 nm.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.