A diode having a simple structure and a simple manufacturing method of the diode are provided. A diode including: a semiconductor layer having a first region and a second region having a resistance lower than a resistance of the first region; a first insulating layer having a first aperture portion and a second aperture portion and covering the semiconductor layer other than the first aperture and the second aperture, the first aperture portion exposing the semiconductor layer in the first region, the second aperture portion exposing the semiconductor layer in the second region; a first conductive layer connected to the semiconductor layer in the first aperture portion and overlapping with the semiconductor layer in the first region via the first insulating layer in a planar view; and a second conductive layer connected to the semiconductor layer in the second aperture.

A semiconductor device includes: a semiconductor base body of a first conductivity-type; a first electrode electrically connected to the semiconductor base body; a first semiconductor region of a second conductivity-type provided at an upper part of the semiconductor base body; a second semiconductor region of the first conductivity-type provided at an upper part of the first semiconductor region; a second electrode electrically connected to the first semiconductor region; an insulating film provided on a top surface of the second semiconductor region; and a passive element provided on a top surface of the insulating film.

A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

A miniaturized transistor having highly stable electrical characteristics is provided. Furthermore, high performance and high reliability of a semiconductor device including the transistor is achieved. The transistor includes a first electrode, a second electrode, a third electrode, an oxide semiconductor layer, a first insulating layer, and a second insulating layer. The transistor includes a first region and a second region surrounded by the first region. In the first region, the first insulating layer, the second electrode, the oxide semiconductor layer, and the second insulating layer are stacked. In the second region, the first electrode, the oxide semiconductor layer, the second insulating layer, and the third electrode are stacked.

An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.

A semiconductor device includes a semiconductor chip having a main surface, a first conductivity type drift region formed in a surface layer portion of the main surface, and a second conductivity type column region formed in a column shape extending in the thickness direction in the drift region, the column region having a lower end portion, an intermediate portion and an upper end portion, wherein the column region has a compensation region including a low concentration portion which is formed between the lower end portion and the intermediate portion, and a high concentration portion which is formed between the intermediate portion and the upper end portion, the compensation region in which a charge balance is compensated within an impurity concentration range between the low concentration portion and the high concentration portion.

A method for manufacturing a power semiconductor device includes: forming a drift region of a first conductivity type, a second emitter region of a second conductivity type, a pn-junction between the second emitter region and drift region, and a first emitter region having a first doping region of the first conductivity type and a second doping region of the first conductivity type; forming a first emitter metallization in contact with the first emitter region to form an ohmic contact between the first emitter metallization and the first doping region, and to form a non-ohmic contact between the first emitter metallization and the second doping region; and forming a second emitter metallization in contact with the second emitter region. The first emitter region is formed using a mask that is aligned with respect to the second emitter region, so that the first and second doping regions are formed in aligned relation.

A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.

A varactor is described that may be constructed in CMOS and has a high tuning range. In some embodiments, the varactor includes a well, a plurality of gates formed over the well and having a capacitive connection to the well, the gates comprising a first subset of the gates that are adjacent and consecutive and coupled to a positive pole of an excitation oscillation signal, and a second subset of the gates that are adjacent and consecutive and coupled to a negative pole of the excitation oscillation signal, and a plurality of source/drain terminals formed over the well and having an ohmic connection to the well, each coupled to a respective gate to receive a control voltage to control the capacitance of the varactor.

A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, and a surface insulating film disposed in a manner extending across the cell portion and the outer peripheral portion, and in the cell portion, formed to be thinner than a part in the outer peripheral portion.