A termination structure for a nitride-based Schottky diode includes a guard ring formed by an epitaxially grown P-type nitride-based compound semiconductor layer and dielectric field plates formed on the guard ring. The termination structure is formed at the edge of the anode electrode of the Schottky diode and has the effect of reducing electric field crowding at the anode electrode edge, especially when the Schottky diode is reverse biased. In one embodiment, the P-type epitaxial layer includes a step recess to further enhance the field spreading effect of the termination structure.

Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

A semiconductor device includes a source region and a drain region formed in a substrate and having different conductivity types, an insulating film formed between the source region and the drain region, a deep well region formed under the insulating film, and a pinch-off region formed under the insulating film and having a same conductivity type as the deep well region, wherein a depth of a bottom surface of the pinch-off region is different from a depth of a bottom surface of the deep well region.

A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

A diode includes an n type semiconductor layer including an n type cathode layer and an n type drift layer that has an impurity concentration lower than the n type cathode layer and that is disposed on the n type cathode layer, a p type anode layer disposed at a surface part of the n type drift layer, a p type hole implantation layer selectively disposed at the n type cathode layer, an anode electrode electrically connected to the p type anode layer, and a cathode electrode electrically connected to the n type cathode layer and to the p type hole implantation layer, and the p type hole implantation layer has a diameter of 20 μm or more.

Lattice-mismatched epitaxial films formed proximate non-crystalline sidewalls. Embodiments of the invention include formation of facets that direct dislocations in the films to the sidewalls.

A semiconductor system including a planar anode contact, a planar cathode contact, and a volume of n-conductive semiconductor material, which has an anode-side end and a cathode-side end and extends between the anode contact and the cathode contact. A p-conductive area extends from the anode-side end of the volume toward the cathode-side end of the volume without reaching the cathode-side end. The p-conductive area has two sub-areas which are separated from one another in a cross section lying transversely with respect to the anode contact and the cathode contact, which delimit a sub-volume of the volume filled with n-conductive semiconductor material. The sub-volume is open toward the cathode contact, and is delimited by cathode-side ends of the sub-areas. A distance of the two sub-areas defining the opening is smaller than a distance between the two sub-areas prevailing outside of the opening and lying between anode side ends of the sub-areas.

A semiconductor device includes a semiconductor layer located between first and second electrodes. The contact location of the semiconductor layer with the first electrode forms a first contact plane. The semiconductor layer includes a first-conductivity-type first semiconductor region in contact with the first electrode, a second-conductivity-type second semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode, a second-conductivity-type third semiconductor region located between the first electrode and the second semiconductor region and contacting the first electrode and having a higher impurity concentration than that of the second semiconductor region, and a second-conductivity-type fourth semiconductor region located between the first electrode and the first semiconductor region and contacting the first electrode. The fourth semiconductor region is narrower than the second semiconductor region, shallower than the second semiconductor region, and has a lower impurity concentration than that of the third semiconductor region.

An impurity of a second conductivity type is selectively doped in a surface of a semiconductor substrate of a first conductivity type to form doped regions. A portion of a surface of the doped regions is covered by a heat insulating film. At least a remaining portion of the surface of the doped regions is covered by an absorbing film and the doped regions are heated through the absorbing film, enabling an impurity region of the second conductivity type to be formed having two or more of the doped regions that have a same impurity concentration and differing carrier concentrations.

A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.