A silicon carbide semiconductor device is a SiC-SBD that has, in an active region, at a front surface of a semiconductor substrate containing silicon carbide, a mixture of a SBD structure having Schottky barrier junctions between a titanium film that is a lowermost layer of a front electrode and an n.sup.−-type drift region, and a JBS structure having pn junction portions between p-type regions and the n.sup.−-type drift region. The p-type regions form ohmic junctions with the titanium film that is the lowermost layer of the front electrode. After an ion implantation for the p-type regions, activation annealing is performed at a temperature in a range of 1700 degrees C. to 1900 degrees C. for a treatment time exceeding 20 minutes, whereby contact resistance between the titanium film and the p-type regions is adjusted to be in a range of about 5×10.sup.−4 Ω.Math.cm.sup.2 to 8×10.sup.−3 Ω.Math.cm.sup.2.

A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.

A nanowire semiconductor device having a high-quality epitaxial layer and a method of manufacturing the same are provided. According to an embodiment, the semiconductor device may include: a substrate; one or more nanowires spaced apart from the substrate, wherein the nanowires each extend along a curved longitudinal extending direction; and one or more semiconductor layers formed around peripheries of the respective nanowires to at least partially surround the respective nanowires, wherein the respective semiconductor layers around the respective nanowires are spaced apart from each other.

Provided is a semiconductor device that includes a semiconductor substrate that is provided with a first conductivity type drift region, a transistor portion that includes a second conductivity type collector region in contact with a lower surface of the semiconductor substrate, and a diode portion that includes a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate, and is alternately disposed with the transistor portion along an arrangement direction in an upper surface of the semiconductor substrate. In the transistor portions, a width in the arrangement direction of two or more transistor portions sequentially selected from the transistor portions nearer to the center in the arrangement direction of the semiconductor substrate is larger than a width in the arrangement direction of one of the other transistor portions.

An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. A first dielectric gate spacer is laterally around the first gate stack and has a portion along an end of the first gate stack and in the gap. A second dielectric gate spacer is laterally around the second gate stack and has a portion along an end of the second gate stack and in the gap. The portion of the second dielectric gate spacer is laterally merged with the portion of the first dielectric gate spacer in the gap.

Conductive via bars self-aligned to gate ends are described. In an example, an integrated circuit structure includes a plurality of gate structures. The integrated circuit structure also includes a plurality of dielectric spacers, a corresponding one of the plurality of dielectric spacers laterally surrounding a corresponding one of the plurality of gate structures. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A conductive via bar is along ends of the plurality of gate structures and ends of the plurality of conductive trench contact structures, wherein the plurality of dielectric spacers is between the ends of the plurality of gate structures and the conductive via bar.

A semiconductor device includes a first junction-gate field-effect transistor (JFET) having a first pinch-off voltage, and a second JFET having a second pinch-off voltage higher than the first pinch-off voltage. The first JFET includes a first top gate region disposed on a surface of a substrate, a first channel region surrounding the first top gate region, and a first bottom gate region disposed under the first channel region. The second JFET includes a second top gate region disposed on the surface and having a same depth with the first top gate region relative to the surface, a second channel region surrounding the second top gate region and disposed deeper than the first channel region relative to the surface, and a second bottom gate region disposed under the second channel region and being deeper than the first bottom gate region relative to the surface.

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure comprising source/drain regions; and at least one isolation structure perpendicular to the at least one gate structure and within the source/drain regions.

A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.