An oxide semiconductor device has an improved withstand voltage when an inverse voltage is applied, while suppressing diffusion of different types of materials to a Schottky interface. The oxide semiconductor device includes an n-type gallium oxide epitaxial layer, p-type oxide semiconductor layers of an oxide that is a different material from the material for the gallium oxide epitaxial layer, a dielectric layer formed to cover at least part of a side surface of the oxide semiconductor layer, an anode electrode, and a cathode electrode. Hetero pn junctions are formed between the lower surfaces of the oxide semiconductor layers and a gallium oxide substrate or between the lower surfaces of the oxide semiconductor layers and the gallium oxide epitaxial layer.

A p-type oxide which is amorphous and is represented by the following compositional formula: xAO.yCu.sub.2O where x denotes a proportion by mole of AO and y denotes a proportion by mole of Cu.sub.2O and x and y satisfy the following expressions: 0x<100 and x+y=100, and A is any one of Mg, Ca, Sr and Ba, or a mixture containing at least one selected from the group consisting of Mg, Ca, Sr and Ba.

A semiconductor device comprising stacked complimentary transistors are described. In some embodiments, the semiconductor device comprises a first device comprising an enhancement mode III-N heterostructure field effect transistor (HFET), and a second device over the first device. In an example, the second device comprises a depletion mode thin film transistor. In an example, a connector is to couple a first terminal of the first device to a first terminal of the second device.

In order to provide a power semiconductor device reducing a leakage current due to a defect layer and having a small fluctuation in a threshold voltage, included are an n-type epitaxial film layer formed on a surface of the single crystal n-type semiconductor substrate and having a concave portion and a convex portion; an insulating film formed on a first region in a top portion of the convex portion; a p-type thin film layer formed on a surface of the insulating film and a surface of the n-type epitaxial film layer to form a pn junction between the p-type thin film layer and the n-type epitaxial film layer; and an anode electrode, at least part of which is formed on a surface of the p-type thin film layer and part of which passes through the p-type thin film layer and the insulating film.

A memristor with a two-dimensional (2D) material heterojunction and a preparation method thereof is provided. The memristor includes a substrate, a bottom electrode layer, a 2D material heterojunction layer and a top electrode layer from bottom to top. The 2D material heterojunction layer serves as an intermediate dielectric layer, and has a two-layer laminate structure composed of two different transitional metal dichalcogenides (TMDCs), with one layer in the laminate structure corresponding to one of the TMDCs. The present invention constructs a novel memristor totally based on 2D materials by improving the materials used for key functional layers in the device and the design for the overall structure of the device. Compared with the prior art, the present invention completely different from the conventional metal/insulator/metal (MIM) structure, and has advantages, such as lower operating voltage, excellent retention and switching stability.

A semiconductor layer of the present invention is a semiconductor layer including: a pn junction at which an n-type semiconductor (Al.sub.2O.sub.3 (n-type)) and a p-type semiconductor (Al.sub.2O.sub.3 (p-type)) are joined, the n-type semiconductor (Al.sub.2O.sub.3 (n-type)) having a donor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain aluminum (Al), the p-type semiconductor (Al.sub.2O.sub.3 (p-type)) having an acceptor level that is formed by causing an aluminum oxide film (Al.sub.2O.sub.3) to excessively contain oxygen (O).

A multi-layer thin film composite is formed by applying a thin film formed from non-single-crystalline oxide onto a substrate; applying a protection film onto the thin film; and supplying energy to the thin film through at least one of the protection film or the substrate.

The present disclosure provides a semiconductor heterojunction. The semiconductor heterojunction includes a bottom semiconductor, a top semiconductor and an electrode substrate. An upper surface of the bottom semiconductor includes a first facet. A lower surface of the top semiconductor includes a second facet, and the lower surface of the top semiconductor is contacted with the upper surface of the bottom semiconductor. The electrode substrate is disposed below the bottom semiconductor.

A power chip, includes a metal region; a wafer region. The wafer region includes at least one first partition, forming a first power switch; and at least one second partition, forming a second power switch. The first power switch and the second power switch are electrically connected, a total number of the at least one first partition and the at least one second partition is not less than 3, and the at least one first partition and the at least one second partition are disposed alternatively along a curve.

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.