H01L29/772

Integrated circuit device with back-side interconnection to deep source/drain semiconductor

Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.

ULTRASENSITIVE BIOSENSOR USING BENT AND CURVED FIELD EFFECT TRANSISTOR BY DEBYE LENGTH MODULATION

Provided are biosensors, systems and related methods of using the biosensors and systems. The biosensor comprises a field-effect transistor (FET) having a crumpled geometry to effectively increase the detection sensitivity of a target molecule in an ionic solution. A FET having a crumpled semiconductor material channel can form a π-π interaction with single stranded DNA (ssDNA) for amplification detection applications. Increasing amount of ssDNA in an amplification reaction solution is incorporated into an amplified double stranded DNA, with increasing amplification, resulting in a lower amount of ssDNA primers. The FET is contacted with the amplified solution to electrically detect an amount of ssDNA primer in the amplified solution, thereby detecting amplification based on a decreased amount of ssDNA bound to the FET. Also provided are biosensors that can detect biomolecules more generally, such as protein, polypeptides, polynucleotides, or small molecules.

ULTRASENSITIVE BIOSENSOR USING BENT AND CURVED FIELD EFFECT TRANSISTOR BY DEBYE LENGTH MODULATION

Provided are biosensors, systems and related methods of using the biosensors and systems. The biosensor comprises a field-effect transistor (FET) having a crumpled geometry to effectively increase the detection sensitivity of a target molecule in an ionic solution. A FET having a crumpled semiconductor material channel can form a π-π interaction with single stranded DNA (ssDNA) for amplification detection applications. Increasing amount of ssDNA in an amplification reaction solution is incorporated into an amplified double stranded DNA, with increasing amplification, resulting in a lower amount of ssDNA primers. The FET is contacted with the amplified solution to electrically detect an amount of ssDNA primer in the amplified solution, thereby detecting amplification based on a decreased amount of ssDNA bound to the FET. Also provided are biosensors that can detect biomolecules more generally, such as protein, polypeptides, polynucleotides, or small molecules.

INTEGRATED CIRCUIT HAVING AN IMPROVED THERMAL INTEGRATED CIRCUIT HAVING AN IMPROVED THERMAL PERFORMANCE
20230207420 · 2023-06-29 ·

An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.

INTEGRATED CIRCUIT HAVING AN IMPROVED THERMAL INTEGRATED CIRCUIT HAVING AN IMPROVED THERMAL PERFORMANCE
20230207420 · 2023-06-29 ·

An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.

Nano-structure assembly and nano-device comprising same
09853106 · 2017-12-26 · ·

Provided are a nano-structure assembly including an insulating substrate; and a nano-structure formed on the insulating substrate, and a nano-device including the same.

Semiconductor device and method of manufacturing the same

An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. The disclosed method comprises forming a wedge-shaped recess with an initial bottom surface in the substrate; transforming the wedge-shaped recess into an enlarged recess with a height greater than the height of the wedge-shaped recess; and epitaxially growing a strained material in the enlarged recess.

Crystalline semiconductor film, plate-like body and semiconductor device
11682702 · 2023-06-20 · ·

A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 μm or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

Transistor with MIS connections and fabricating process

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.

Transistor with MIS connections and fabricating process

A field-effect transistor, including a source, drain and channel formed in a semiconductor layer a gate stack placed above the channel, including a metal electrode, a first layer of electrical insulator placed between the metal electrode and the channel, and a second layer of electrical insulator covering the metal electrode; a metal contact placed plumb with the source or drain and at least partially plumb with said gate stack; and a third layer of electrical insulator placed between said metal contact and said source or said drain.