A bulk acoustic wave resonator and a method of manufacturing the same are provided. The bulk acoustic wave resonator includes: a first carrier substrate; a barrier layer on a main surface of the first carrier substrate and configured to prevent an undesired conductive channel from being generated due to charge accumulation on the main surface; a buffer layer on a side of the barrier layer away from the first carrier substrate; a piezoelectric layer on a side of the buffer layer away from the barrier layer; a first electrode and a second electrode on opposite sides of the piezoelectric layer; a first passivation layer and a second passivation layer, respectively covering sidewalls of the first electrode and the second electrode; a dielectric layer between the first passivation layer and the buffer layer, wherein a first cavity is provided between the first passivation layer and the dielectric layer.

A package substrate with an embedded device and a manufacturing method therefor are disclosed. The method includes: manufacturing a third circuit layer and a target on a temporary carrier plate, and laminating a third dielectric layer; placing a device to be embedded on the third dielectric layer which is then covered with a second dielectric layer; laminating a second copper foil and manufacturing a second circuit layer, a second copper pillar, and a third copper pillar; laminating a first dielectric layer and a first copper foil sequentially, and removing the temporary carrier plate; laminating a fourth dielectric layer on the third circuit layer; laminating a fourth copper foil on the fourth dielectric layer; and manufacturing a fourth circuit layer and a fourth copper pillar through the fourth copper foil, and manufacturing a first circuit layer and a first copper pillar through the first copper foil.

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

A carbon nanotube structure includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes. And a heat dissipation sheet includes a plurality of carbon nanotube structures arranged in a sheet form, wherein each of the carbon nanotube structures includes a plurality of carbon nanotubes, and a graphite film that binds one ends of the plurality of carbon nanotubes.

A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes. The decrease in the bonding area also makes it possible to correspondingly improve the reproducibility of forming the diameter of the electrodes, and make reliable connection possible.

A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed.