Provided is a plating apparatus for plating a substrate by using a substrate holder including an elastic projection that seals a to-be-plated surface of the substrate, the plating apparatus comprising a measurement device configured to measure a deformed state of the elastic projection by measuring at least either one of a compression amount of the elastic projection and load applied to the elastic projection at a time when the substrate physically contacts the elastic projection of the substrate holder; and a controlling device configured to make a judgment on the basis of the measured deformed state as to whether sealing by the elastic projection is normal.

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

The present disclosure provides a method for measuring an underfill profile of an underfill material in an underfill cavity having a plurality of solder bumps. The method includes the operations of: determining a mesh having a plurality of elements according to the underfill cavity; calculating a reference force according to the underfill cavity; obtaining a driving force and a flow speed of the underfill material according to a plurality of weighting factors and the reference force, wherein the plurality of weighting factors respectively correspond to the plurality of elements; obtaining a plurality of volume fractions respectively corresponding to the plurality of elements according to the flow speed; and obtaining the underfill profile according to the plurality of volume fractions.

The embodiments of the disclosure provide a manufacturing method of a package circuit, including the following steps. A circuit structure including a plurality of conductive pads is formed. A liquid crystal layer is formed on the circuit structure. An inspection step is performed, and the inspection step includes determining the conductivity of the conductive pads according to the result of the rotation of a liquid crystal layer oriented with an electric field. In addition, the liquid crystal layer is removed.

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

The present invention comprises an arrangement and process for the fluxless manufacture of an integrated circuit component, comprising the steps of loading a solder ball and chip arrangement, solder ball side up or down, onto a first or a second donor chuck respectively; monitoring the solder ball and chip arrangement by a computer-controlled camera; removing the solder ball and chip arrangement from the donor chuck by a computer-controlled gripper mechanism; moving the solder ball and chip arrangement via the gripper mechanism onto a computer-controlled gang carrier, the monitored by a second computer controlled camera; flipping the gang carrier about a horizontal axis so as to arrange the solder ball and chip arrangement into an inverted, solder ball side down orientation over a receiver chuck substrate, monitored and positionally controlled by a third computer-controlled camera; and compressing the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate by a computer-controlled compression rod so as to bond the solder ball side down solder ball and chip arrangement onto the receiver chuck substrate so as to form an integrated circuit assembly.

A method of electroplating a metal into features, having substantially different depths, of a partially fabricated electronic device on a substrate is provided. The method includes adsorbing accelerator into the bottom of recessed features; partially filling the features by a bottom up fill mechanism in an electroplating solution; diffusing leveler into shallow features to decrease the plating rate in shallow features as compared to deep features; and electroplating more metal into the features such that the height of metal in deep features is similar to the height of metal in shallow features.

A method for printing solder onto a wafer (101) including the steps of depositing solder paste (102) onto a wafer (101), applying an inline reflow process to the deposited solder paste (102) to form solder bumps (103) on the wafer (101), and cleaning the reflowed solder bumps (103). The method for printing solder onto the wafer (101) is based on a system thereof that includes a wafer solder printer (1), an inline reflow means (2) and a de-fluxing means (3), wherein each step has its parameters optimized by means of a staging process control.

A unitary wafer assembly arrangement for the application of solder balls onto a substrate for subsequent use in the electronics industry. This wafer tool assembly comprises a number of modules connected to one another and all serviced by a robotic arm to transfer processed wafers from one module to another. The tool assembly comprises a load port and pre-aligner module, a binder module, a solder ball mount module and a reflow module. A wafer inspection and repair module arrangement is also part of the tool assembly.

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.