A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.

The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.

The present invention provides a test pad structure of chip, which comprises a plurality of first internal test pads, a plurality of second internal test pads, a plurality of first extended test pads, and a plurality of second extended test pads. The first internal test pads and the second internal test pads are disposed in a chip. The second internal test pads and the first internal test pads are spaced by a distance. The first extended test pads are connected with the first internal test pads. The second extended test pads are connected with the second internal test pads. The first extended test pads and the second extended test pads may increase the contact area to be contacted by probes. Signals or power are transmitted to the first internal test pads and the second internal test pads via the first extended test pads and the second extended test pads for the probes to test the chip.

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.

A semiconductor device having a capillary flow structure for a direct chip attachment is provided herein. The semiconductor device generally includes a substrate and a semiconductor die having a conductive pillar electrically coupled to the substrate. The front side of the semiconductor die may be spaced a distance apart from the substrate forming a gap. The semiconductor device further includes first and second elongate capillary flow structures projecting from the front side of the semiconductor die at least partially extending toward the substrate. The first and second elongate capillary flow structures may be spaced apart from each other at a first width configured to induce capillary flow of an underfill material along a length of the first and second elongate capillary flow structures. The first and second capillary flow structures may include pairs of elongate capillary flow structures forming passageways therebetween to induce capillary flow at an increased flow rate.

Provided are a display panel, a preparation method thereof, and a display device. The display panel includes a plurality of sub-panels. Each sub-panel includes first substrate, second substrate, bezel adhesive located therebetween, a plurality of bank structures, and a plurality of light-emitting elements. At least one light-emitting element forms a pixel unit. Each bank structure is located between adjacent pixel units. Seaming adhesive is located between adjacent sub-panels. The sub-panels share a same first substrate, and the seaming adhesive is disposed on the same first substrate. The first substrate includes a display region and a non-display region surrounding the display region. The light-emitting elements and the bank structures are located in the display region, and the bezel adhesive is located in the non-display region. In this manner, splicing gaps between adjacent sub-panels can be effectively reduced, and thus the display effect of the display panel can be improved.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.

The present invention provides a flow guiding structure of chip, which comprises at least one flow guiding member disposed on a surface of a chip and adjacent to a plurality of connecting bumps disposed on the surface of the chip. When the chip is disposed on a board member, the at least one flow guiding member may guide the conductive medium on the surface of the chip to flow toward the connecting bumps and drive a plurality of conductive particles of the conductive medium to move toward the connecting bumps and thus increasing the number of the conductive particles on the surfaces of the connecting bumps. Alternatively, the flow guiding member may retard the flow of the conductive medium for avoiding the conductive particles from leaving the surfaces of the connecting bumps and thus preventing reduction of the number of the conductive particles on the surfaces of the connecting bumps.