The present invention relates to a ceramic substrate for a power module, a method for manufacturing same, and a power module having same, the power module electrically connecting, by means of a conductive spacer, an electrode of a semiconductor device and a metal layer pattern of a ceramic substrate without a wire, thereby converting rated voltage and current while removing electrical risk factors, which may be generated during wire bonding, and increasing reliability and efficiency when used with high power.

Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.

A printable component includes a component substrate and one or more electrical conductors. One or more electrically conductive connection posts protrudes from the component substrate to form an exposed electrical contact. Each connection post is electrically connected to at least one of the electrical conductors and one or more wicking posts protrude from the component substrate. The wicking post can be insulating. In certain embodiments, a printable component source wafer comprises a source wafer, a plurality of sacrificial portions separated by anchor portions formed in a sacrificial layer of the source wafer, and a plurality of printable components. Each printable component is disposed over a corresponding sacrificial portion and connected to an anchor portion by a tether. A destination substrate structure comprises a destination substrate having one or more electrically conductive contact pads, an adhesive layer disposed on the destination substrate, and one or more printable components.

A semiconductor package includes a substrate, a first semiconductor chip on the substrate and including a first chip pad and a first upper insulating layer on sidewalls of the first chip pad, a first bonding wire on a top surface of the first chip pad and connected to the first chip pad, and a second semiconductor chip on a top surface of the first semiconductor chip and spaced apart from the first chip pad, wherein the second semiconductor chip includes a second semiconductor die and a second lower insulating layer on a bottom surface of the second semiconductor die, wherein the second lower insulating layer may be directly bonded to the first upper insulating layer by a chemical bond between the first upper insulating layer and the second lower insulating layer.

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

Anisotropic conductive film (ACF) structures and manufacturing methods for forming the same are described. The manufacturing methods include preventing clusters of conductive particles from forming between adjacent bonding pads and that are associated with electrical shorting of ACF structures. In some embodiments, the methods involve use of multiple layered ACF materials that include a non-electrically conductive layer that reduces the likelihood of formation of conductive particle clusters between bonding pads. In some embodiment, the methods include the use of ultraviolet sensitive ACF material combined with lithography techniques that eliminate conductive particles from between neighboring bonding pads. In some embodiments, the methods involve the use of insulation spacers that block conductive particles from entering between bonding pads. Any suitable combination of the described methods can be used.

In a semiconductor device, a semiconductor element includes a semiconductor substrate and an upper electrode on a first surface of the semiconductor substrate. The semiconductor substrate has an IGBT region and a diode region. An upper conductor is disposed to face the upper electrode. An upper solder is interposed between the upper electrode and the upper conductor. An alloy layer is interposed between the upper electrode and the upper solder. The upper electrode includes an Al electrode disposed on the first surface and an Ni electrode disposed on the Al electrode. The upper solder contains Cu and Sn. The alloy layer contains Ni, Cu, and Sn. At least in a region overlapping with the diode region in a plan view along a thickness direction of the semiconductor substrate, a grain size of the upper solder is smaller on the semiconductor element side than on the upper conductor side.

An electronic module includes: an electronic element that has an electrode; an internal connection terminal having conductivity that is electrically connected to the electrode of the electronic element; and a spacer that is disposed between the internal connection terminal and the electronic element, wherein a conductive bonding material is disposed between the internal connection terminal and the spacer, and a protruding portion is formed on a surface of the internal connection terminal on an electronic element side, and a distal end of the protruding portion is brought into contact with an upper surface of the spacer.

A power module includes an upper substrate, a lower substrate, a first semiconductor chip, a first spacer electrically interconnecting a first metal layer of the upper substrate and a second metal layer of the lower substrate, a second spacer electrically interconnecting the first semiconductor chip and the first metal layer, and a first connection layer configured to form a current path, and a power lead.

A semiconductor device including a substrate, a semiconductor package, a thermal conductive bonding layer, and a lid is provided. The semiconductor package is disposed on the substrate. The thermal conductive bonding layer is disposed on the semiconductor package. The lid is attached to the thermal conductive bonding layer and covers the semiconductor package to prevent coolant from contacting the semiconductor package.