The present disclosure describes a semiconductor device including: a semiconductor chip having an electrode; a conductive member including a metal base and having a mounting portion and a peripheral portion surrounding the mounting portion; a solder that is provided between the electrode and the mounting portion; and a sealing resin body that integrally seals the semiconductor chip, at least the face opposed to the electrode in the conductive member, and the solder.

A first inner heat conductor may include a plurality of first graphite layers. A second inner heat conductor may include a plurality of second graphite layers. The plurality of first graphite layers may be stacked in a first direction which is orthogonal to a direction in which a semiconductor element and a first heat radiator are arranged. The plurality of second graphite layers may be stacked in the direction in which the semiconductor element and the first heat radiator are arranged, or may be stacked in a second direction which is orthogonal to the direction in which the semiconductor element and the first heat radiator are arranged and orthogonal to the first direction.

A semiconductor device may include a semiconductor element; a temperature detecting element provided at a central part of a surface of the semiconductor element, and a heat conductor jointed to the surface of the semiconductor element via a jointing element. The jointing element may include a central part positioned over the temperature detecting element, and a peripheral part positioned on a periphery of the central part of the jointing element. The heat conductor may include a metal part being in contact with the central part of the jointing element, and a graphite part being in contact with the peripheral part of the jointing element.

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

A semiconductor device includes a first semiconductor module and a second semiconductor module. The first semiconductor module configures an upper arm, and includes first semiconductor elements connected in parallel to each other, a sealing resin body, and a positive electrode terminal. The second semiconductor module configures a lower arm, and includes second semiconductor elements connected in parallel to each other, a sealing resin body, and a negative electrode terminal. The first and second semiconductor modules are aligned in an alignment direction. At least one of the first and second semiconductor modules has a relay terminal for electrically relaying electrodes on a low potential side of the first semiconductor elements and electrodes on a high potential side of the second semiconductor elements.

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate, a second conductor layer and a third conductor layer wherein a hole is formed in the second insulating substrate, the second conductor layer has a bonding portion and a surrounding wall portion; an inner resin portion; a control IC; and an outer resin portion, wherein the first substrate, the power device part, the second substrate and the control IC are stacked in this order, a connector is disposed in the inside of the hole, and the gate electrode is electrically connected to a control signal output terminal of the control IC through a connector.

Provided are a semiconductor device which is provided with a circuit board and capable of suppressing an increase in its footprint, and a power conversion apparatus including the semiconductor device. The semiconductor device includes a circuit board, a power semiconductor element, an insulating block, a control signal terminal, a first main terminal, and a second main terminal. The insulating block is disposed so as to surround the power semiconductor element. The control signal terminal is inserted into the insulating block and thereby fixed to the insulating block. The control signal terminal includes a bent portion which partially protrudes above the power semiconductor element from the insulating block, and is bonded to the power semiconductor element. The first main terminal is bonded to the same power semiconductor element as the power semiconductor element to which the control signal terminal is bonded. The second main terminal is bonded to the circuit board.

The present invention relates to a printed circuit board embedding a power die wherein interconnections between the power die and the printed circuit board are composed of micro/nano wires, the printed circuit board comprising a cavity wherein the power die is placed, and wherein the cavity is further filled with a dielectric fluid.

A cooler includes a coolant flow path between a first cooling plate and a second cooling plate segmented into a plurality of flow path segments along a flow-path traverse direction. The plurality of flow path segments includes at least one first flow path segment and at least one second flow path segment. Each first flow path segment includes: a first inner plate partitioning an internal space thereof into a first space and a second space and having a first nozzle that jets the coolant from the first space toward the second cooling plate. Each second flow path segment includes: a second inner plate partitioning an internal space thereof into a first space and a second space and having a second nozzle that jets the coolant from the second space toward the first cooling plate. The first inner and second inner plates are aligned in the flow-path traverse direction.

A power semiconductor device having a high degree of reliability even when an operable temperature of a power semiconductor element is sufficiently increased. The power semiconductor device includes: a power semiconductor element including an electrode formed on a first surface; a first stress mitigation portion connected to the electrode with a first bonding portion being interposed; and a wiring portion electrically connected to the first stress mitigation portion with a second bonding portion being interposed. A bonding strength of the first bonding portion is higher than a bonding strength of the second bonding portion.