A semiconductor package includes a metal baseplate, first and second HEMT dies each including a main surface with source, drain and gate terminals disposed thereon, a plurality of metal package terminals, and an encapsulant body of electrically insulating material, wherein the first and second HEMT dies are mounted on the metal baseplate with the main surfaces from each of the first and second HEMT dies facing away from the metal baseplate, wherein the encapsulant body encapsulates the first and second HEMT dies, wherein outer ends from each of the metal package terminals are exposed from the encapsulant body, and wherein each of the source, drain and gate terminals from the first and second HEMT dies is electrically connected via a bond wire-free connection to at least one of the metal package terminals.

A method of making a plurality of integrated circuit (IC) packages includes picking up a plurality of physically unconnected IC components; and simultaneously placing each of the physically unconnected IC components on corresponding portions of an unsingulated IC package strip that includes a sheet of integrally connected leadframes.

To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

A method for forming a panel of stacked semiconductor packages includes providing a bottom leadframe (LF) panel including LFs downset each including at least a plurality of terminals. Low side (LS) transistors are attached to the first die attach area. A first clip panel including first clips downset and interconnected are placed on the bottom LF panel. A dielectric interposer is attached on the first clips over the LS transistors. High side (HS) transistors are attached on the interposers. A second clip panel including a plurality of second clips is mated to interconnect to the HS transistors including mating together the second clip panel, first clip panel and bottom LF panel. The LFs can include a second die attach area, and a controller die attached on the second die attach area, and then pads of the controller die wirebonded to the plurality of terminals.

A semiconductor package includes a first metal plate having a first surface, a semiconductor chip including a first electrode and a second electrode, on the first surface, and a second metal plate on the semiconductor chip. The first metal plate has a first surface. The first electrode is connected to the first metal plate. The second metal plate includes a second surface and first and second side surfaces respectively on opposite sides of the second metal plate and connected to the second surface. The first side surface has a first recessed portion extending in a direction which crosses the first and second surfaces, and the second side surface has a second recessed portion extending in the second direction that crosses the first and second surfaces.

A power module includes a substrate, a plurality of semiconductor dies coupled to the substrate, and a clip substrate member having a first surface and a second surface. The first surface is coupled to the plurality of semiconductor dies. The clip substrate member includes a first conductive clip, and a second conductive clip, and a dielectric material portion disposed between the first conductive clip and the second conductive clip. The second surface includes a first contact region and a second contact region. The first contact region includes a portion of the first conductive clip. The second contact region includes a portion of the second conductive clip.

A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

System, method, and silicon chip package for providing structural strength, heat dissipation and electrical connectivity using W shaped frame bonded to the one or more dies, wherein the W shaped frame provides compression strength to the silicon chip package when the one or more dies are bonded, and electrically conductivity between for the one or more dies to leads of silicon chip package, and heat dissipation for the silicon chip package.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.

A method for forming packaged electronic devices includes providing a substrate having pads connected by conductive pad linking portions and semiconductor devices attached to the pads in different orientations. A second substrate is provided having conductive connectors each with a plate portion, a conductive member extending from a side segment of the plate portion, a connective portion extending from the conductive member distal to the plate portion, and conductive linking portions physically connecting adjoining plate portions together. Each plate portion is attached to one of the semiconductor devices to provide a subassembly. A package body is provided to encapsulate at least portions of the subassembly. The method includes separating the encapsulated subassembly to provide the packaged electronic devices such that the separating step severs the conductive linking portions.