A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.

A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element.

A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.

A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material. A top surface of the first semiconductor chip and a top surface of the first molding layer are flat and are coplanar with each other, and a ratio of the difference between the coefficient of thermal expansion between the second molding layer and the first molding layer to the difference between the coefficient of thermal expansion between the second molding layer and the substrate is between 5:1 and 20:1.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.