Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

A method for bonding a contact surface of a first substrate to a contact surface of a second substrate comprising of the steps of: positioning the first substrate on a first receiving surface of a first receiving apparatus and positioning the second substrate on a second receiving surface of a second receiving apparatus; establishing contact of the contact surfaces at a bond initiation site; and bonding the first substrate to the second substrate along a bonding wave which is travelling from the bond initiation site to the side edges of the substrates, wherein the first substrate and/or the second substrate is/are deformed for alignment of the contact surfaces.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.