Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures. After the following batch annealing, the fill nanoporous metal layer turns into pure bulk metal same as conductive interconnect structures due to the heat expansion of conductive interconnect structures and nanoporous metal densification.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.

A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

In a method for manufacturing a semiconductor device, a first structure is formed on a first substrate. A first bonded body is formed by bonding a supporting substrate to a first principal surface, on which the first structure is formed, of the first substrate. The supporting substrate is higher in rigidity than the first substrate. The first substrate is removed from the first bonded body. A second structure is formed on a second substrate. A third structure is formed on a third substrate. A second bonded body is formed by bonding a second principal surface, on which the second structure is formed, of the second substrate to a third principal surface, on which the third structure is formed, of the third substrate. The third substrate is removed from the second bonded body. A third bonded body is formed by bonding a fourth principal surface, which is exposed after the first substrate is removed, of the first bonded body to a fifth principal surface, which is exposed after the third substrate is removed, of the second bonded body. The supporting substrate is removed from the third bonded body.

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.

A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.