A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.

A semiconductor device is provided, including a first die, such as a GaN HEMT die, and a second die, such as a MOSFET die, with the second die positioned on the top of the first die. The second die is attached using a die attach adhesive. The semiconductor device further includes an encapsulant deposited on the top of the semiconductor device. The encapsulant is covering the first die and the second die. Metalized vias are created within the encapsulant, and the metalized vias are arranged to distribute terminals of the first die and the terminals of the second die to the top side of the semiconductor device.

A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.

A micro-component module comprises a module substrate, a component disposed on the module substrate, and at least a portion of a module tether in contact with the module substrate. The module substrate can be flexible or can comprise an organic material, or both. The module tether can be more brittle and less flexible than the module substrate. The component can be less flexible than the module substrate and can comprise at least a portion of a component tether. An encapsulation layer can be disposed over the component and module substrate. The component can be disposed in a mechanically neutral stress plane of the micro-component module. A micro-component module system can comprise a micro-component module disposed on a flexible system substrate, for example by micro-transfer printing. A micro-component module can comprise an internal module cavity in the module substrate with internal module tethers physically connecting the module substrate to internal anchors.

Provided is a method for forming a conductive feature including forming a seed layer over a substrate; forming a patterned mask layer on the seed layer, wherein the patterned mask layer has an opening exposing the seed layer; forming a conductive material in the opening; removing the patterned mask layer to expose a portion of the seed layer; and removing the portion of the seed layer by using an etching solution including a protective agent, thereby forming a conductive feature, wherein the protective agent has multiple active sites to adsorb on the conductive material.

A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

An example of a printable electronic component includes a component substrate having a connection post side and an opposing contact pad side. The component can include one or more non-planar, electrically conductive connection posts protruding from the connection post side of the component substrate. Each of the one or more connection posts can have a peak area smaller than a base area. The component can include one or more non-planar, electrically conductive exposed component contact pads disposed on (e.g., directly on, indirectly on, or in) the contact pad side of the component substrate. Multiple components can be stacked such that connection post(s) of one are in contact with non-planar contact(s) of one or more others.

An embedded module according to the present invention includes a base substrate having a multi-layer wiring, at least two semiconductor chip elements having different element thicknesses, each of the semiconductor chip element having a first surface fixed to the base substrate and having a connection part on a second surface, an insulating photosensitive resin layer enclosing the semiconductor chip elements on the base substrate and being formed by a first wiring photo via, a second wiring photo via, and a wiring, the first wiring photo via electrically connected to the connection part of the semiconductor chip elements, the second wiring photo via arranged at the outer periphery of each of the semiconductor chip elements and electrically connected to a connection part of the base substrate, the wiring arranged so as to be orthogonal to and electrically connected to the first wiring photo via and the second wiring photo via.

Packaging methods for semiconductor devices, packaged semiconductor devices, and design methods thereof are disclosed. In some embodiments, a method of packaging a plurality of semiconductor devices includes providing a first die, and coupling second dies to the first die. An electrical connection is formed between the first die and each of the second dies. A portion of each of the electrical connections is disposed between the second dies.

Disclosed are a triode packaging method and a triode. The method includes: providing a carrier, and covering at least one surface of the carrier with a surface metal layer; covering a circuit pattern region of the surface metal layer with a resist film; electroplating a non-circuit pattern region of the surface metal layer, to form at least one first bonding pad; welding a chip on the at least one first bonding pad; welding a second bonding pad on the chip to form a triode template; performing plastic packaging on the triode template by using a composite material; drilling blind holes in vertical directions of the second bonding pad and the at least one first bonding pad, and processing the blind holes into metallic blind holes; and performing pattern fabrication on the metallic blind holes to form a closed-circuit loop or a non-closed-circuit loop, and obtaining a triode through packaging.