Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

A method and corresponding device for permanent bonding of a first layer of a first substrate to a second layer of a second substrate on a bond interface, characterized in that a dislocation density of a dislocation of the first and/or second layer is increased at least in the region of the bond interface before and/or during the boding.

Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

In the present disclosure, a first semiconductor element of a bonded structure comprises a semiconductor-containing oxynitride bonding layer formed on a first substrate layer comprising a semiconductor material, e.g., a single crystal silicon. The semiconductor-containing oxynitride bonding layer is formed by exposing an upper surface of the first substrate layer to products of plasma containing nitrogen and oxygen at controlled plasma conditions. The second semiconductor element of the bonded structure may have a second substrate layer comprising a semiconductor material, e.g., a single crystal silicon, and a semiconductor-containing oxynitride bonding layer formed over the second substrate layer in the same way as the first semiconductor element. In some embodiments, the second semiconductor element may have a bonding layer comprising a dielectric material. After initial direct bonding of the first and second semiconductor elements, the bonded structure may go through an annealing process to strengthen the bonding.

A semiconductor device including: a die paddle having an upper surface; a solder layer disposed on the upper surface of the die paddle; and a die disposed on the solder layer, so that the solder layer is between the die paddle and the die; the solder layer includes a plurality of spacers configured to be, during production of the semiconductor device prior to hardening of the solder layer, movable in relation to the die paddle; and the die paddle includes a plurality of recesses in the upper surface of the die paddle, and the plurality of recesses is configured to receive the plurality of spacers, so that the plurality of spacers is embedded within the plurality of recesses.