A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes placing a first semiconductor chip on a carrier with the first main surface of the first semiconductor chip facing the carrier. A first layer of soft solder material is provided between the first main surface and the carrier. Heat is applied during placing so that a temperature at the first layer of soft solder material is equal to or higher than a melting temperature of the first layer of soft solder material. A second layer of soft solder material is provided between the first contact area and the second main surface. Heat is applied during placing so that a temperature at the second layer of soft solder material is equal to or higher than a melting temperature of the second layer of soft solder material. The first and second layers of soft solder material are cooled to solidify the soft solder materials.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

Provided is a flip chip mounting apparatus for mounting chips (400) to a substrate (200), and the apparatus includes at least one sectionalized mounting stage (45) divided into a heating section (452) and a non-heating section (456), the heating section being for heating a substrate (200) fixed to a front surface of the heating section, the non-heating section not heating the substrate (200) suctioned to a front surface of the non-heating section. With this, it is possible to provide an electronic-component mounting apparatus that is simple and capable of efficiently mounting a large number of electronic components.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.

A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the nanoparticle preform is placed on a substrate and a workpiece is placed on the nanoparticle preform.

A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.

Method for manufacturing an RFID tag comprising an IC and an antenna. The method comprising the steps of providing an antenna made of a soldering material, which antenna is at least partly covered with a hot melt adhesive in solid form; heating the antenna to a temperature above its melting point, wherein the heated parts of the antenna and the hot melt adhesive melt, placing an IC in a predetermined position which position is suitable for the IC to connect to the antenna; pressing the IC and antenna together, such that, an electrical connection between the IC and the antenna is established; and cooling RFID tag, such that the hot melt adhesive and the antenna solidify, wherein a soldered joint between the IC and the antenna is achieved and the hot melt adhesive surrounds the joint between the IC and the antenna.

In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.