A method is provided to fabricate a high-power module. A non-touching needle is used to paste a slurry on a heat-dissipation substrate. The slurry comprises nano-silver particles and micron silver particles. The ratio of the two silver particles is 9:1˜1:1. The slurry is pasted on the substrate to be heated up to a temperature kept holding. An integrated chip (IC) is put above the substrate to form a combined piece. A hot presser processes thermocompression to the combined piece to form a thermal-interface-material (TIM) layer with the IC and the substrate. After heat treatment, the TIM contains more than 99 percent of pure silver with only a small amount of organic matter. No volatile organic compounds would be generated after a long term of use. No intermetallic compounds would be generated while the stability under high temperature is obtained. Consequently, embrittlement owing to procedure temperature is dismissed.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

An arrangement includes a chamber, a heating element arranged in the chamber, wherein the heating element, when a first connection partner with a pre-connection layer formed thereon is arranged in the chamber, is configured to heat the first connection partner and the pre-connection layer, thereby melting the pre-connection layer, and a cooling trap. During the process of heating the first connection partner with the pre-connection layer formed thereon, the cooling trap has a temperature that is lower than the temperature of all other components of or in the chamber such that liquid evaporating from the pre-connection layer is attracted by and condenses on the cooling trap.

The present invention provides a method for producing a semiconductor device, including: a semiconductor chip-mounting step of subsequently pressing a plurality of semiconductor chips by a first pressing member to respectively bond the plurality of semiconductor chips to a plurality of mounting areas provided on a substrate, wherein the bonding is performed in a state where adhesive sheets are respectively interposed between the plurality of semiconductor chips and the plurality of mounting areas, each of the adhesive sheets includes sinterable metal particles that can be sintered by heating at a temperature of 400° C. or less, and the first pressing member is heated to a temperature, at which the sinterable metal particles can be sintered.

A method of manufacturing a substrate layered body includes: a step of applying a bonding material to the surface of at least one of a first substrate or a second substrate; a step of curing the bonding material applied on the surface to form a bonding layer having a reduced modulus at 23° C. of 10 GPa or less; and a step of bonding the first substrate and the second substrate via the bonding layer formed.

A method of manufacturing a semiconductor device which includes a plurality of members including a semiconductor element is provided. The method may include disposing one surface of a first member which is one of the plurality of members and one surface of a second member which is another one of the plurality of members opposite to each other with a tin-based (Sn-based) solder material interposed therebetween, and bonding the first member and the second member by melting and solidifying the Sn-based solder material. At least the one surface of the first member may be constituted of a nickel-based (Ni-based) metal, and at least the one surface of the second member may be constituted of copper (Cu).

The invention relates to display device and method of manufacturing the same. The display device includes: a substrate; a driving pad disposed on the substrate; an insulating layer exposing the driving pad and disposed on the substrate; a circuit board including a circuit pad overlapping the driving pad; and a connector disposed between the circuit board and the insulating layer and including a plurality of conductive particles electrically connecting the driving pad and the circuit pad, the driving pad including: a first pad disposed on the substrate; and a second pad disposed on the first pad and having an opening exposing the first pad.

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

Embodiments of the present disclosure include method for sequentially mounting multiple semiconductor devices onto a substrate having a composite metal structure on both the semiconductor devices and the substrate for improved process tolerance and reduced device distances without thermal interference. The mounting process causes “selective” intermixing between the metal layers on the devices and the substrate and increases the melting point of the resulting alloy materials.

A power semiconductor device includes a substrate and a semiconductor element bonded onto a first surface of the substrate through use of a sintered metal bonding material. The substrate has a plurality of dimples formed in the first surface and located outside a location immediately below a heat generation unit of the semiconductor element. The sintered metal bonding material is supplied onto the substrate after the formation of the dimples, and the semiconductor element is bonded to the substrate through application of heat and a pressure thereto.