An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

Provided is an adhesive composition for multilayer semiconductors. The adhesive composition gives, when applied and dried by heating, an adhesive layer that has approximately no adhesiveness at a temperature lower than 50 C., but, when heated at such a temperature as to less cause damage to semiconductor chips, offers adhesiveness and is rapidly cured thereafter. This adhesive composition for multilayer semiconductors includes a polymerizable compound (A), at least one of a cationic-polymerization initiator (B1) and an anionic-polymerization initiator (B2), and a solvent (C). The polymerizable compound (A) contains 80% by weight or more of an epoxide having a softening point or melting point of 50 C. or higher. The cationic-polymerization initiator (B1) gives a composition having a thermal curing time of 3.5 minutes or longer at 130 C., where the composition contains 1 part by weight of the cationic-polymerization initiator (B1) and 100 parts by weight of 3,4-epoxycyclohexylmethyl (3,4-epoxy)cyclohexanecarboxylate. The anionic-polymerization initiator (B2) gives a composition having a thermal curing time of 3.5 minutes or longer at 130 C., where the composition contains 1 part by weight of the anionic-polymerization initiator (B2) and 100 parts by weight of bisphenol-A diglycidyl ether.

The invention relates to a positioning device for positioning a substrate, in particular a wafer, comprising: a process chamber; a base body; a carrier element which comprises a support for supporting the substrate, the carrier element being arranged above the base body and formed movable in terms of distance from the base body; and a holder for an additional substrate, in particular an additional wafer or a mask, the holder being arranged opposite the carrier element; wherein there is, between the base body and the carrier element, a sealed-off cavity to which a pressure, in particular a negative pressure, can be applied so as to prevent undesired movement of the carrier element as a result of the action of an external force.

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.

A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

A bonding member (10) includes surface-processed silver surfaces (11a, 11b).

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.