The present invention is an IC chip mounting apparatus including: an ejection unit configured to eject an adhesive toward a reference position of each antenna of an antenna continuous body, the antenna continuous body having a base material and plural inlay antennas continuously formed on the base material; a nozzle movable between a first position and a second position, the nozzle being configured to suck an IC chip, when located at the first position, and to place the IC chip on the adhesive at the reference position of each antenna, when located at the second position; a determination unit configured to determine whether an IC chip is sucked by the nozzle while the nozzle is moved from the first position to the second position; and a moving machine configured to move the nozzle away from the second position when it is determined by the determination unit that an IC chip is not sucked by the nozzle.

A semiconductor device includes a substrate and a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the inactive surface. The stepped side surfaces include a first planar surface extending from the inactive surface towards the active surface, a second planar surface extending from the active surface towards the inactive surface, and a side surface offset between the first planar surface and the second planar surface. The semiconductor device further includes an adhesive layer covering at least a portion of a surface area of the second surface and attaching the semiconductor die to the substrate.

In one embodiment, methods for making semiconductor devices are disclosed.

A die placement system provides a tip body and die placement head to ensure planarity of a die to substrate without the need for calibration prior to each pick and place operation. A self-aligning tip incorporated into a tip body aids in die placement/attachment. This tip provides for global correction of planarity errors that exist between a die and substrate, regardless of whether those errors stem from gantry (i.e. die-side misalignment) or machine deck tool (i.e. substrate-side misalignment) misalignment.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

Methods for attachment and devices produced using such methods are disclosed. In certain examples, the method comprises disposing a capped nanomaterial on a substrate, disposing a die on the disposed capped nanomaterial, drying the disposed capped nanomaterial and the disposed die, and sintering the dried disposed die and the dried capped nanomaterial at a temperature of 300° C. or less to attach the die to the substrate. Devices produced using the methods are also described.

Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.

A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.