The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

A composite assembly of three stacked joining partners, and a corresponding method. The three stacked joining partners are materially bonded to one another by an upper solder layer and a lower solder layer. An upper joining partner and a lower joining partner are fixed in their height and have a specified distance from one another. The upper solder layer is fashioned from a first solder agent, having a first melt temperature, between the upper joining partner and a middle joining partner. The second solder layer is fashioned from a second solder agent, having a higher, second melt temperature, between the middle joining partner and the lower joining partner. The upper joining partner has an upwardly open solder compensating opening filled with the first solder agent, from which, to fill the gap between the upper joining partner and the middle joining partner, the first solder agent subsequently flows into the gap.

A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.

A system includes a semiconductor substrate having a first cavity. The semiconductor substrate forms a pedestal adjacent the first cavity. A device overlays the pedestal and is bonded to the semiconductor substrate by metal within the first cavity. A plurality of second cavities are formed in a surface of the pedestal beneath the device, wherein the second cavities are smaller than the first cavity. In some of these teachings, the second cavities are voids. In some of these teachings, the metal in the first cavity comprises a eutectic mixture. The structure relates to a method of manufacturing in which a layer providing a mask to etch the first cavity is segmented to enable easy removal of the mask-providing layer from the area over the pedestal.

A light emitting diode (LED) includes a n-doped semiconductor material layer, a p-doped semiconductor material layer, an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer, and a photonic crystal grating configured to increase the light extraction efficiency of the LED.

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

A semiconductor device includes a first die; a second die attached over the first die; a metal enclosure directly contacting and extending between the first die and the second die, wherein the first metal enclosure is continuous and encircles a set of one or more internal interconnects, wherein the first metal enclosure is configured to electrically connect to a first voltage level; and a second metal enclosure directly contacting and extending between the first die and the second die, wherein the second metal enclosure is continuous and encircles the first metal enclosure and is configured to electrically connect to a second voltage level; wherein the first metal enclosure and the second metal enclosure are configured to provide an enclosure capacitance encircling the set of one or more internal interconnects for shielding signals on the set of one or more internal interconnects.