Planar, double-side cooled half-bridge power modules using sintered-silver interposers and all sintered-silver joints are described. Thermo-mechanical simulations showed that use of the sintered-silver interposers reduce the thermo-mechanical stresses at vulnerable interfaces as compared to using solid copper interposers. The porous sintered-silver interposers are also easily deformable under a low load, which improves the yield of module interconnections in the presence of imperfections caused by variations in die thickness, interposer height, and substrate distortion. Results on the electrical performance of the modules validate the fabrication approach for the modules, for making high power-density converters with reliable operations at high junction temperatures.

Described examples include a device including a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of the surface area of the second surface. The adhesive layer includes first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous. The first polymeric compound has a first modulus and the second polymeric compound has a second modulus greater than the first modulus.

A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board.

In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

Provided is a bonding joining structure in which a heat generating body and a support including a metal are joined to each other via a joint portion composed of a sintered body of copper powder. The support contains copper or gold, the copper or gold being present in at least an outermost surface of the support. An interdiffusion portion in which copper or gold contained in the support and copper contained in the sintered body is formed so as to straddle a bonding interface between the support and the sintered body. Preferably, a copper crystal structure having the same crystal orientation is formed in the interdiffusion portion so as to straddle the bonding interface.

An electronic sandwich structure which has at least a first and a second part to be joined, which are sintered together by means of a sintering layer. The sintering layer is formed as a substantially uninterrupted connecting layer, the density of which varies in such a way that at least one region of higher density and at least one region of lower density alternate with one another. A method for forming a sintering layer of an electronic sandwich structure, in which firstly a sintering material layer is applied substantially continuously to a first part to be joined as a connecting layer, this sintering material layer is subsequently dried and, finally, alternating regions of higher density and of lower density of the connecting layer are produced by sintering the first part to be joined with the sintering layer on a second part to be joined.

A semiconductor device vertically mounted on a medium such as a printed circuit board, and a method of its manufacture, are disclosed. The semiconductor device includes a stack of semiconductor die having contact pads which extend to an active edge of the die aligned on one side of the stack. The active edges of the die are affixed to the PCB and the contact pads at the active edge are electrically coupled to the PCB. This configuration provides an optimal, high density arrangement of semiconductor die in the device, where a large number of semiconductor die can be mounted and electrically coupled directly to the PCT, without a substrate, without staggering the semiconductor die, and without using wire bonds.

Integrated active-matrix multi-color light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. An example integrated device includes a backplane device and different color light emitting diodes (LEDs) devices arranged in different height planar layers on the backplane device. The backplane device includes at least one backplane having a number of pixel circuits. Each LED device includes an array of LEDs each operable to emit light with a particular color and conductively coupled to respective pixel circuits in the backplane to form active-matrix LED sub-pixels. The different color LED sub-pixels form an array of active-matrix multi-color display pixels. Plug vias can be arranged in different planar layers to conductively couple upper-level LEDs to respective pixel circuits in respective regions over the backplane device. The plug vias can extend from an upper planar layer into a lower planar layer to fix the two planar layers together.

A method of attaching a semiconductor die or chip onto a support member such as a leadframe comprises: applying onto the support member at least one stretch of ribbon electrical bonding material and coupling the ribbon material to the support member, arranging at least one semiconductor die onto the ribbon material with the ribbon material between the support member and the semiconductor die, coupling the semiconductor die to the ribbon material.

A semiconductor device includes a metal chip mounting member and a semiconductor chip bonded to the chip mounting member through a metal sintered material, wherein the metal sintered material includes a first portion overlapping the semiconductor chip in a plan view, and includes a second portion surrounding the semiconductor chip in the plan view, and wherein a porosity ratio of the first portion is greater than or equal to 1% and less than 15%, and a porosity ratio of the second portion is greater than or equal to 15% and less than or equal to 50%.