Patent classifications
H01L2224/83201
LASER BONDING METHOD AND A SEMICONDUCTOR PACKAGE INCLUDING A BONDING PART AND A BONDING TARGET
Provides is a laser bonding method. The method includes forming a bonding part on a substrate; aligning a bonding target on the bonding part and bonding the bonding part and the bonding target. The bonding includes heating the bonding part using a laser. The bonding part formed on the substrate includes an adhesive layer and a conductive particle located in the adhesive layer.
Electronic device having conductive particle between pads
An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.
Electronic device having conductive particle between pads
An electronic device includes a substrate, a first pad disposed on the substrate, a second pad disposed opposite to the first pad, and a conductive particle disposed between the first pad and the second pad. The first pad has a recess, and a part of the conductive particle sinks in the recess.
FLIP CHIP BONDING METHOD AND CHIP USED THEREIN
In a bonding process of a flip chip bonding method, a chip is bonded to contact pads of a substrate by composite bumps which each includes a raiser, a UBM layer and a bonding layer. Before the bonding process, the surface of the bonding layer facing toward the substrate is referred to as a surface to be bonded. During the bonding process, the surface to be bonded is boned to the contact pad and become a bonding surface on the contact pad. The bonding surface has an area greater than that of the surface to be bonded so as to reduce electrical impedance between the chip and the substrate.
Process and device for low-temperature pressure sintering
Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.
Method for forming a pre-connection layer on a surface of a connection partner and method for monitoring a connection process
A method for forming a connection between two connection partners includes: forming a pre-connection layer on a first surface of a first connection partner, the pre-connection layer including a certain amount of liquid; performing a pre-connection process, thereby removing liquid from the pre-connection layer; performing photometric measurements while performing the pre-connection process, wherein performing the photometric measurements includes determining at least one photometric parameter of the pre-connection layer, wherein the at least one photometric parameter changes depending on the fluid content of the pre-connection layer; and constantly evaluating the at least one photometric parameter, wherein the pre-connection process is terminated when the at least one photometric parameter is detected to be within a desired range.
Method for forming a pre-connection layer on a surface of a connection partner and method for monitoring a connection process
A method for forming a connection between two connection partners includes: forming a pre-connection layer on a first surface of a first connection partner, the pre-connection layer including a certain amount of liquid; performing a pre-connection process, thereby removing liquid from the pre-connection layer; performing photometric measurements while performing the pre-connection process, wherein performing the photometric measurements includes determining at least one photometric parameter of the pre-connection layer, wherein the at least one photometric parameter changes depending on the fluid content of the pre-connection layer; and constantly evaluating the at least one photometric parameter, wherein the pre-connection process is terminated when the at least one photometric parameter is detected to be within a desired range.
Method and structure to control the solder thickness for double sided cooling power module
In a soldering structure, a power module having the same, and a method for manufacturing the power module configured for constantly determining a height of a power module when the power module is manufactured, the soldering structure may include a soldering target portion; a metal layer including a bonding surface having a bonding region in which the soldering target portion is bonded by solder; and at least one wire located in the solder within the bonding region.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD
When a semiconductor unit is heated, a heater having a flat heating surface is used for performing heating in a state in which a lower surface of an insulated circuit board is placed on the heating surface. When the semiconductor unit is cooled, a cooler having a cooling surface including a pair of support portions is used for performing cooling in which a lower surface of a pair of outer regions of the insulated circuit board are respectively placed to be contact with the pair of support portions, and in which a central region between the pair of outer regions of the insulated circuit board is pressed downward so as to be downward convex.
SEMICONDUCTOR DIE, A SEMICONDUCTOR DIE STACK, A SEMICONDUCTOR MODULE, AND METHODS OF FORMING THE SEMICONDUCTOR DIE AND THE SEMICONDUCTOR DIE STACK
A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.