A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 m and less than or equal to 0.8 m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 m and less than or equal to 50 m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300 C., and a content of the solvent having a boiling point of higher than or equal to 300 C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

A copper paste for pressureless bonding is a copper paste for pressureless bonding, containing: metal particles; and a dispersion medium, in which the metal particles include sub-micro copper particles having a volume average particle diameter of greater than or equal to 0.01 m and less than or equal to 0.8 m, and micro copper particles having a volume average particle diameter of greater than or equal to 2.0 m and less than or equal to 50 m, and the dispersion medium contains a solvent having a boiling point of higher than or equal to 300 C., and a content of the solvent having a boiling point of higher than or equal to 300 C. is greater than or equal to 2 mass % on the basis of a total mass of the copper paste for pressureless bonding.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface.

A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the second insulating plate and the second semiconductor chip, a third bonding material provided between the second metal plate and the second semiconductor chip, the third bonding material bonding the second metal plate and the second semiconductor chip, a fourth bonding material provided between the second base material and the second insulating plate, the fourth bonding material bonding the second base material and the second insulating plate, and a first base bonding portion provided between the second side surface and the first side surface and bonded to the first side surface and the second side surface.

A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.