A method includes providing a first part, a second part and a bonding material between the first part and the second part. The first part and the second part are made of a first material selected from a group consisting of silicon and germanium. The bonding material includes a second material that is different than the first material. The method includes arranging the first part, the bonding material, and the second part in a furnace; and creating a bonded part by heating the first part, the second part and the bonding material to a predetermined temperature for a predetermined period followed by a predetermined solidification period. The predetermined temperature is greater than 1.5 times a eutectic temperature of an alloy including the first material and the second material and less than a melting temperature of the first material.

An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Provided is an inkjet adhesive which is applied using an inkjet device, wherein the adhesive can suppress generation of voids in the adhesive layer and, after bonding, can reduce an outgas at the time of being exposed to high temperatures, and can enhance moisture-resistant reliability. An inkjet adhesive according to the present invention comprises a first photocurable compound having one (meth)acrylol group, a second photocurable compound having two or more (meth)acrylol groups, a photo-radical initiator, a thermosetting compound having one or more cyclic ether groups or cyclic thioether groups, and a compound capable of reacting with the thermosetting compound, and the first photocurable compound contains alkyl (meth)acrylate having 8 to 21 carbon atoms.

A method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

According to a method for producing a circuit carrier arrangement, a carrier which has a surface section formed by an aluminum/silicon carbide metal matrix composite material is provided. A circuit carrier, which has an insulation carrier with a lower side onto which a lower metallization layer is applied, is also provided. A bonding layer, which contains a glass, is generated on the surface section. A material-fit connection between the bonding layer and the circuit carrier is produced by means of a connecting layer.

Some embodiments include a method. The method can comprise: providing a carrier substrate; providing an adhesion modification layer over the carrier substrate; providing a device substrate; and coupling the device substrate and the carrier substrate together, the adhesion modification layer being located between the device substrate and the carrier substrate when the device substrate and the carrier substrate are coupled together. In these embodiments, the adhesion modification layer can be configured so that the device substrate couples indirectly with the carrier substrate by way of the adhesion modification layer with a first bonding force that is greater than a second bonding force by which the device substrate couples with the carrier substrate absent the adhesion modification layer. Other embodiments of related methods and devices are also disclosed.

An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.