The present disclosure provides a method of creating a bond between a first object and a second object. For example, creating a joint or die attach between a semiconductor chip and an electronic substrate, especially for harsh and high temperature environments. The method may include a step of filling a space between the first object and the second object with a filler material. Further, the method may include a step of heating the filler material to facilitate formation of a plurality of inter-diffusion layers. Accordingly, a first inter-diffusion layer may be formed between the filler material and the first object. Further, a second inter-diffusion layer may be formed between the filler material and the second object. Furthermore, in some embodiments, the first inter-diffusion layer may be contiguous with the second inter-diffusion layer. The contiguity may be facilitated by placement of at least one insert between the first object and the second object, in which the inter-diffusion of the filler material and the at least one insert may produce the third inter-diffusion layer, wherein the third inter-diffusion layer is contiguous with each of the first inter-diffusion layer and the second inter-diffusion layer.

A process of forming a semiconductor device is disclosed, where the semiconductor device provides a substrate. The process includes steps of: (a) depositing a first metal layer containing nickel (Ni) on a secondary surface of the substrate and within a substrate via provided in the substrate; (b) depositing a second metal layer on the first metal layer by electrolytic plating; (c) depositing a third metal layer on the second metal layer, where the third metal layer contains at least one of Ni and titanium (Ti); (d) exposing the second metal layer in a portion that excepts the substrate via and a periphery of the substrate via by partly removing the third metal layer; and (e) die-bonding the semiconductor device on an assembly substrate by interposing solder between the secondary surface of the substrate and the assembly substrate.

A manufacturing method of a semiconductor apparatus includes preparing an intermediate member that includes a first member having a first substrate comprising a semiconductor element formed thereon, a second member having a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from that of the first substrate, and a third member having a third substrate showing such a linear expansion coefficient that a difference between itself and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficients of the first substrate and the second substrate, and includes bonding the first member and the second member together. A first bonding electrode containing copper electrically connected to the semiconductor element and a second bonding electrode containing copper electrically connected to the circuit are bonded together.

A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 m to 10 m. A method of manufacturing a metal surface with such micropores also is described.

The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.

A sintered member is provided between a semiconductor chip and a terminal. The sintered member is made of a sinter sheet by heating and pressing the same. The semiconductor chip is connected to the terminal via the sintered member. Convex portions are formed at a front-side surface of the semiconductor chip. Concave portions, each of which has such a shape corresponding to that of each convex portion of the semiconductor chip, are formed at a surface of the sintered member facing to the semiconductor chip.

In one example, a semiconductor device, comprises a substrate having a top side and a conductor on the top side of the substrate, an electronic device on the top side of the substrate connected to the conductor on the top side of the substrate via an internal interconnect, a lid covering a top side of the electronic device, and a thermal material between the top side of the electronic device and the lid, wherein the lid has a through-hole. Other examples and related methods are also disclosed herein.

Disclosed is a method that includes: providing semiconductor dies, each of the semiconductor dies having a thinner active region surrounded by a thicker inactive region so that each of the semiconductor dies has a first cavity vertically aligned with the thinner active region and laterally surrounded by the thicker inactive region; providing a metal carrier having connection parts secured to the metal carrier, each of the connection parts dimensioned to fit within the first cavity of one of the semiconductor dies; inserting each of the connection parts of the metal carrier into the respective first cavity of the corresponding semiconductor die; after the inserting, attaching the metal carrier to the semiconductor dies; and after the attaching, singulating the metal carrier so that each of the connection parts of the metal carrier remains attached to the corresponding semiconductor die.

An LED chip provided by an embodiment includes a first semiconductor layer; an active layer and a second semiconductor layer located sequentially on the first semiconductor layer. A first contact electrode extends through the active layer and the second semiconductor layer and is electrically connected to the first semiconductor layer; a second contact electrode is located on the second semiconductor layer and is electrically connected to the second semiconductor layer; a first extension electrode is located on the first contact electrode and is electrically connected to the first contact electrode, the first extension electrode comprises a plurality of concave spots for soldering; and a second extension electrode is located on the second contact electrode, electrically connected to the second contact electrode and isolated from the first extension electrode, and the second extension electrode includes a plurality of concave spots for soldering.

In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.