A semiconductor module bonding structure includes: a semiconductor module including a semiconductor element and a positive terminal which is a plate-shaped power terminal electrically connected to the semiconductor element; and a main P bus bar which is a bus bar including a plate-shaped bonding part bonded to the positive terminal of the semiconductor module. The positive terminal of the semiconductor module which is one of the positive terminal and the bonding part of the main P bus bar that has a relatively small thickness is configures to be wider than the bonding part which is the other having a relatively large thickness, and the positive terminal and the bonding part are bonded together by fusion welding in the state of being arranged so that the respective thickness directions of the positive terminal and the bonding part are orthogonal to each other.

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Concepts as well as arrangements are suggested, according to which a bond is enabled by anodic bonding between a glass substrate (200) having contact vias (210) and a substrate (100) including a semiconductor. For this purpose, a cover of the contact vias (210) is provided during the anodic bonding method such that process conditions are created that achieve a reliable and robust bonding of the substrates. A high resistance can be provided in the region of the contact vias (210). The arrangement for contacting the semiconductor device to the silicon substrate (100) having at least one contact via (210) extending through the passivation in order to contact a region of the first substrate (100).

A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

A die-to-wafer stacking method includes: providing a wafer to be processed, including a substrate, a dielectric layer on the substrate and a metal layer embedded in the dielectric layer; forming a bonding layer covering the dielectric layer; picking up dies to be bonded from the wafer to be processed and arranging the dies to be bonded on an electrostatic chuck; and bonding the dies arranged on the electrostatic chuck, as a whole, to a wafer to be bonded. Pre-arranging all the dies to be bonded on the electrostatic chuck and then bonding the dies on the electrostatic chuck, as a whole, to the wafer to be bonded can greatly shorten post-activation waiting times of dies before they are bonded to the wafer and thus reduce the risk of loss of activation.

A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus. In some cases, the leveling adjustment system may include a plurality of threaded posts, differentially threaded adjustment collars, and leveling sleeves. In some instances, the leveling adjustment system further may include a plurality of preload springs configured to provide a given preload capacity and range of adjustment. In some instances, the leveling adjustment system further may include a load cell through which one of the threaded posts may be inserted. In some embodiments, the upper block assembly further may include a reaction plate configured to reduce deformation of the upper block assembly. In some embodiments, the upper block assembly further may include a thermal isolation plate configured to provide compliance deflection and being of monolithic or polylithic construction, as desired.

A semiconductor device including a first lead electrode and a second lead electrode on a lead frame; a semiconductor stack structure disposed on the lead frame, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a conductive adhesive configured to bond the semiconductor stack structure to the lead frame; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure.

Methods for preparing layered semiconductor structures are disclosed. The methods may involve pretreating an ion-implanted donor wafer by annealing the ion-implanted donor wafer to cause a portion of the ions to out-diffuse prior to wafer bonding. The donor structure may be bonded to a handle structure and cleaved without re-implanting ions into the donor structure.