The present invention relates to a method of forming a joint bonding together two solid objects and joints made by the method, where the joint is formed by a layer of a binary system which upon heat treatment forms a porous, coherent and continuous single solid-solution phase extending across a bonding layer of the joint.

Provided are a device packing facility and method using phthalate and a device processing apparatus utilizing the phthalate. The device packaging facility includes a mounting unit providing phthalate between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the phthalate and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.

Process for producing an electronic subassembly by low-temperature pressure sintering, comprising the following steps: arranging an electronic component on a circuit carrier having a conductor track, connecting the electronic component to the circuit carrier by the low-temperature pressure sintering of a joining material which connects the electronic component to the circuit carrier, characterized in that, to avoid the oxidation of the electronic component or of the conductor track, the low-temperature pressure sintering is carried out in a low-oxygen atmosphere having a relative oxygen content of 0.005 to 0.3%.

A semiconductor device includes a substrate, a semiconductor element and a tin-based solder layer. The semiconductor element faces the substrate in a normal direction of the substrate. The normal direction corresponds to a normal line of the substrate. The tin-based solder layer joins the semiconductor element to the substrate. The tin-based solder layer a central portion and a peripheral portion surrounding the central portion. The tin-based solder layer has a tin crystal with a C-axis at each of the central portion and the peripheral portion. The C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line. The C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.

A semiconductor device includes a substrate, a semiconductor element and a tin-based solder layer. The semiconductor element faces the substrate in a normal direction of the substrate. The normal direction corresponds to a normal line of the substrate. The tin-based solder layer joins the semiconductor element to the substrate. The tin-based solder layer a central portion and a peripheral portion surrounding the central portion. The tin-based solder layer has a tin crystal with a C-axis at each of the central portion and the peripheral portion. The C-axis at the central portion intersects the normal line at an angle larger than 45 degrees with respect to the normal line. The C-axis at the peripheral portion either intersects the normal line at an angle smaller than or equal to 45 degrees with respect to the normal line, or is parallel to the normal line.

A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.

The present invention provides a method for producing a semiconductor device, including: a semiconductor chip-mounting step of subsequently pressing a plurality of semiconductor chips by a first pressing member to respectively bond the plurality of semiconductor chips to a plurality of mounting areas provided on a substrate, wherein the bonding is performed in a state where adhesive sheets are respectively interposed between the plurality of semiconductor chips and the plurality of mounting areas, each of the adhesive sheets includes sinterable metal particles that can be sintered by heating at a temperature of 400° C. or less, and the first pressing member is heated to a temperature, at which the sinterable metal particles can be sintered.

Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.