A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.

A chip bonding apparatus includes: a bonding contact configured to apply a bonding force to a semiconductor chip disposed on a substrate, the bonding contact having a first surface configured to face the semiconductor chip and a second surface opposite the first surface, the bonding contact including a protruding portion on the first surface, the protruding portion configured to contact the semiconductor chip, the bonding contact including a cavity formed in a region vertically overlapping the protruding portion, a heater disposed to be in contact with the second surface of the bonding contact to cover the cavity, and configured to heat the bonding contact, a bonding head disposed above the heater and configured to transmit the bonding force, and a partition wall structure protruding from a bottom surface of the cavity to partition an inner space of the cavity.

The present publication discloses a method for manufacturing a circuit-board structure. In the method, a conductor layer is made, which comprises a conductor foil and a conductor pattern on the surface of the conductor foil. A component is attached to the conductor layer and the conductor layer is thinned, in such a way that the conductor material of the conductor layer is removed from outside the conductor pattern.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.

A thermosetting composition for use as an underfill material contains: a mono- or bifunctional acrylic compound; a thermo-radical polymerization initiator; silica; and an elastomer including a 1,2-vinyl group. The thermosetting composition is liquid and has a property of turning, when cured thermally, into a cured product having a relative dielectric constant of 3.2 or less at 25° C. and a dielectric loss tangent of 0.013 or less at 25° C.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Structures and methods are disclosed for fabricating optoelectronic solid state array devices. In one case a backplane and array of micro devices is aligned and connected through bumps.