An integrated circuit package, a die carrier, and a die are provided. The die carrier includes at least one die pad and a plurality of leads. The at least one die pad is suitable for carrying the die. The leads surround the at least one die pad. The leads are disposed on four sides of the die carrier. A length of a long side among the four sides is twice or more a length of a short side among the four sides. The die carrier is suitable for a QFN package or a QFP package.

Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

A semiconductor package is disclosed. The package includes a package substrate having top and bottom major package substrate surfaces, the top major package surface including a die region. A die having first and second major die surfaces is attached onto the die region. The second major die surface is attached to the die region. The first major die surface includes a sensor region and a cover adhesive region surrounding the sensor region. The package also includes applying a cover adhesive to the cover adhesive region on the first major die surface. A protective cover with first and second major cover surfaces and side surfaces is attached to the die using the cover adhesive. The second major cover surface contacts the cover adhesive. The protective cover covers the sensor region. The protective cover includes a recessed structure on the second major cover surface. The recessed structure is located above die bond pads on the die to create an elevated space over peak portions of wire bonds on the die bond pads. An encapsulant is disposed on the package substrate to cover exposed portions of the package substrate, die and bond wires and side surfaces of the protective cover, while leaving the first major cover surface exposed.

Disclosed is a wire bonding apparatus comprising a capillary, a wire clamp assembly, and a support. The wire clamp assembly includes a first member, a second member, a first contact member, and a second contact member. The first member includes a first body and a first tilting member. The second member includes a second body and a second tilting member. The first contact member is coupled to an inner surface of the first tilting member and extends in an extending direction of the first tilting member. The second contact member is coupled to an inner surface of the second tilting member and extends in an extending direction of the second tilting member. The second member is movable in the second direction.

An electronic component package has an outer edge including a first side and a second side adjacent to each other. The electronic component package includes a first electronic component chip, a second electronic component chip provided at a distance from the first electronic component chip, one or more first terminals disposed along the first side, one or more second terminals disposed along the second side, and one or more first conductors. The one or more first conductors couple the one or more first terminals to the first electronic component chip, with the one or more first terminals being uncoupled to the second electronic component chip.

The present disclosure provides a semiconductor structure including a substrate, a first die vertically over the substrate, a second die vertically over the substrate and laterally separated from the first die with a gap, and an insulation material in the gap. The substrate is at least partially overlapped with the gap when viewed from a top view perspective, and a Young's modulus of the substrate is higher than that of the insulation material.

A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.

Disclosed is a wire bonding apparatus comprising a capillary, a wire clamp assembly, and a support. The wire clamp assembly includes a first member, a second member, a first contact member, and a second contact member. The first member includes a first body and a first tilting member. The second member includes a second body and a second tilting member. The first contact member is coupled to an inner surface of the first tilting member and extends in an extending direction of the first tilting member. The second contact member is coupled to an inner surface of the second tilting member and extends in an extending direction of the second tilting member. The second member is movable in the second direction.

A semiconductor device includes: a first chip including a first electrode; a wiring member; a second chip located between the first chip and the wiring member, including a second electrode; a first conductive plate located on the first electrode, in a second direction a dimension of the first conductive plate being greater than a dimension of the first chip, the second direction crossing a first direction being from the first chip toward the second chip; a second conductive plate located on the second electrode, in a second direction a dimension of the second conductive plate being greater than a dimension of the second chip; and a first wire being bonded to the wiring member, a portion of the first conductive plate protruding further in the second direction than the first chip, and a portion of the second conductive plate protruding further in the second direction than the second chip.

A semiconductor device and associated methods are disclosed. In one example, dies are interconnected through a bridge in a substrate. A reference voltage stack extends over at least a portion of the interconnect bridge, and a passive component is coupled to the reference voltage stack. In one example, the passive component helps to reduce interference in the power supply to components in the semiconductor device, such as the dies and the interconnect bridge.