Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, and a molding layer. The semiconductor chip includes a circuit region and an edge region around the circuit region. The molding layer covers a sidewall of the semiconductor chip. The semiconductor chip includes a reforming layer on the edge region. A top surface of the reforming layer is coplanar with a top surface of the molding layer.

A semiconductor package may include; a first substrate, a first semiconductor chip disposed on the first substrate, an interposer disposed on the first semiconductor chip, a connecter spaced apart from the first semiconductor chip in a first horizontal direction and extending between the first substrate and the interposer, wherein the connecter directly electrically connects the first substrate and the interposer, a capacitor disposed between the connecter and the first semiconductor chip, and a guide pattern including a first guide portion and an opposing second guide portion spaced apart in the first horizontal direction, wherein the first guide portion is disposed between the connecter and the capacitor, the second guide portion is disposed between the capacitor and the first semiconductor chip, and at least part of the capacitor is inserted between the first guide portion and the second guide portion.

A semiconductor device includes a substrate, an electronic component, a cover and a liquid metal. The electronic component is disposed on the substrate. The cover is disposed on the substrate and covers the electronic component. The liquid metal is formed between the cover and the electronic component.

A method includes attaching an integrated circuit chip module substrate to a printed circuit board (PCB). First region(s) of a bottom surface of the module include electrical contacts to the board, and second region(s) of the bottom surface of the module lack such contacts. Mechanical structures are assembled into the second regions. These structures allow lateral motion of the module relative to the board, and are sized and placed to inhibit bending of the second regions of the module towards the board under application of a vertical force on a top surface of the module. A package for an integrated circuit may be assembled using the method.

In one example, a semiconductor package comprises a substrate having a top surface and a bottom surface, an electronic device mounted on the top surface of the substrate and coupled to one or more interconnects on the bottom surface of the substrate, a cover over the electronic device, a casing around a periphery of the cover, and an encapsulant between the cover and the casing and the substrate.

A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.

A semiconductor package includes an interposer; a first stacked chip including a first semiconductor chip disposed on the interposer and one or more second semiconductor chips disposed on the first semiconductor chip; a first molding layer surrounding the first stacked chip; and a second molding layer surrounding the first molding layer, wherein the second molding layer extends from an uppermost surface of the interposer to a trench of the interposer.

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

A semiconductor device includes a first heat sink formed in contact with a back surface of a first semiconductor chip, and a second heat sink formed in contact with a back surface of a second semiconductor chip. The first heat sink is made of a material with larger thermal conductivity than that of the first semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside. The second heat sink is made of a material with larger thermal conductivity than that of the second semiconductor chip and has a heat dissipation surface exposed from the mold resin layer to the outside.

Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.