Systems and methods of the disclosed subject matter for converting light into electrical signals are provided including receiving light input and outputting electrical signals proportional to the light input with a sensor, increasing a transimpedance gain of an amplifier to amplify the electrical signals with a T-network of resistors coupled to the amplifier and the sensor, filtering the electrical signals with a filter circuit coupled to the amplifier and the T-network of resistors to increase noise rejection in a predetermined frequency range, and outputting the filtered electrical signals.

Systems and methods of the disclosed subject matter for converting light into electrical signals are provided including receiving light input and outputting electrical signals proportional to the light input with a sensor, increasing a transimpedance gain of an amplifier to amplify the electrical signals with a T-network of resistors coupled to the amplifier and the sensor, filtering the electrical signals with a filter circuit coupled to the amplifier and the T-network of resistors to increase noise rejection in a predetermined frequency range, and outputting the filtered electrical signals.

A single-ended to differential conversion circuit for converting an input signal into a pair of differential signals is provided. An amplifier includes an inverting input terminal, a non-inverting input terminal for receiving a reference signal, and an output terminal. A first resistor is coupled between the inverting input terminal and the output terminal of the amplifier. A second resistor is coupled to the inverting input terminal of the amplifier. The third resistor is coupled to the output terminal of the amplifier. The resistor string is coupled between the output terminal of the amplifier and the second resistor, and includes a fourth resistor and a fifth resistor connected in series. A signal of the pair of differential signals is provided via the third resistor, and another signal of the pair of differential signals is provided via the resistor string.

An instrumentation amplifier (INA) that includes a first amplifier and a second amplifier coupled to the first amplifier. The first amplifier includes a first transistor. The first amplifier is configured to receive a positive phase signal of a differential signal. The second amplifier includes a second transistor and is configured to receive a negative phase signal of the differential signal. The first and second transistors each include a gate, source, and drain. The first transistor drain is connected to the second transistor drain.

A microphone preamplifier circuit is adapted to be connected to a microphone circuit, the microphone circuit including a microphone and at least one output node. The microphone preamplifier circuit includes a preamplifier including: an operational amplifier having at least one input and at least one output; at least one input DC decoupling capacitor connected to the at least one input of the operational amplifier; at least one feedback capacitor connected between the input and the output of the operational amplifier in order to set together with the at least one input DC decoupling capacitor a gain value of the preamplifier circuit; and first and second feed nodes adapted to be fed by first and second bias voltages respectively. The preamplifier further includes at least one switched capacitor adapted to be selectively and alternatively connected in response to a clock signal: between the at least one input and the at least one output of the operational amplifier; and between the first and second feed nodes. The microphone preamplifier circuit further includes an anti-aliasing filter having: (i) at least one output terminal connected to the at least one input DC decoupling capacitor and (ii) at least one input terminal adapted to be connected to the at least one output node of the microphone circuit.

A neuron recording system was provided. By using the gain-boosted topology, the amplifier input impedance can be increased while simultaneously reducing the noise. The system can be configured to record local field potentials (LFPs) and neuron spikes, respectively, with low-power consumption. With the flexible digital controller module (DCM), any subset of the recording channels can be activated for recording with independent sampling rate at each channel. A wireless interface to transmit recorded neuron data and an on-chip neuron processor to perform real-time signal processing can be incorporated in the system.

An amplifier circuit (1) for amplifying an audio signal, includes: an input stage (I) for receiving a first input signal representing the audio signal; a transformer (T) including a primary winding (L.sub.1) and a secondary winding (L.sub.2), defining a first terminal, a second terminal and a middle terminal; a differential amplifier (U), having a first input (U.sub.+), connected to the first terminal of the secondary winding (L.sub.2); a second input (U.sub.), connected to the middle terminal of the secondary winding (L.sub.2), and an output (U.sub.out), connected to the second terminal of the secondary winding (L.sub.2); an additional transformer (T) including an additional primary winding (L.sub.1) and secondary winding (L.sub.2), defining a first terminal, a second terminal and a middle terminal; an additional differential amplifier (U), having a first input (U.sub.+), connected to the first terminal of the additional secondary winding (L.sub.2), a second input (U.sub.+) connected to the middle terminal of the additional secondary winding (L.sub.2) and an output (U.sub.out) connected to the second terminal of the additional secondary winding (L.sub.2); an output circuit (O) for receiving as input the output signals from the differential amplifier (U) and from the additional differential amplifier (U) to generate a differential output signal (V.sub.out).

A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.

A semiconductor device has an amplifier and common mode suppression (CMS) circuit formed on a common substrate. The CMS circuit has a first input and second input coupled for receiving an input signal and further has a first output coupled to a first input of the amplifier and a second output coupled to a second input of the amplifier to reduce common mode. The CMS circuit further has a ground plane, a first conductive trace disposed over the ground plane and coupled between the first input and first output, second conductive trace disposed over the ground plane and coupled between the second input and second output, and third conductive trace disposed over the ground plane with a first end of the third conductive trace coupled to the ground plane and a second end of the third conductive trace open circuit to form a resonator.

A differential input stage includes first and second input transistors with current flow paths are coupled between a tail transistor current flow path and first and second nodes, respectively. An output stage includes first and second output transistors having current flow paths between a supply line and first and second output nodes, respectively, coupled to the first and second nodes. First and second common-mode control transistors have current flow paths jointly coupled to a ground current flow path of a common-mode tail transistor. The first common-mode control transistor has a control terminal resistively coupled to the first and second output nodes. A bias duplicate transistor has a current flow path arranged in a bias current flow line between the supply line and ground. The bias duplicate transistor is coupled in a 1:N current mirror arrangement with the tail transistor in the differential input stage.