A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

Input bits are encoded into codewords that include coded bits. Encoding involves applying a first set of polar encoding matrices G.sub.Y of prime number dimension Y to the input bits to produce output bits, and applying a second set of polar encoding matrices G.sub.Z of prime number dimension Z to the output bits to produce the codeword. One or both of G.sub.X and G.sub.Y could be non-2-by-2. Such kernel design and other aspects of code construction, including reliabilities and selection of sub-channels for code construction, non-CRC-aided error correction, and code shortening and puncturing, are discussed in further detail herein.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

A transceiver architectures can contain an encoder and a decoder for communicating high speed transmissions. The encoder can modulate signal data for being mapped in a constellation that is generated based on concatenations of an E8 lattice having binary and non-binary codes. The data can be transmitted at a high speed according to the constellation with an embedded E8 lattice configuration in order to generate a coding gain. A decoder operates to decode the received input signal data with a decreased latency or a minimal latency with a high spectral efficiency.

The disclosed embodiments provide a memory system that provides error detection and correction. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C-M-1 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and M inner check bit columns that collectively include MR inner check bits. These inner check bits are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is associated with a different pin in a memory module interface, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors that arise during the transmission. During operation, the system transmits a block of data from the memory. Next, the system uses an error-detection circuit to examine the block of data, and determine whether an error has occurred during the transmission based on the examination.

An apparatus for polar coding includes an encoder circuit that implements a transformation c=u.sub.1.sup.N-sB.sub.N-s{tilde over (M)}.sub.n, where u.sub.1.sup.N-s, B.sub.N-s, {tilde over (M)}.sub.n, and C are defined over a Galois field GF(2.sup.k), k>1, N=2.sup.k, s<N, u.sub.1.sup.N-s=(u.sub.1, . . . , u.sub.N-s) is an input vector of N-s symbols over GF(2.sup.k), B.sub.N-s is a permutation matrix, {tilde over (M)}.sub.n=((Ns) rows of M.sub.n=), the matrix M.sub.1 is a pre-defined matrix of size qq, 2<q, N=q.sup.n and n1, and C is a codeword vector of N-s symbols. A decoding complexity of C is proportional to a number of symbols in C. The apparatus further includes a transmitter circuit that transmits codeword C over a transmission channel.

A distributed storage system can use a high rate MSR erasure code to repair multiple nodes when multiple node failures occur. An encoder constructs m r-ary trees to determine the symbol arrays for the parity nodes. These symbol arrays are used to generate the parity data according to parity definitions or parity equations. The m r-ary trees are also used to identify a set of recovery rows across helper nodes for repairing a systematic node. When failed systematic nodes correspond to different ones of the m r-ary trees, a decoder may select additional recovery rows. The decoder selects additional recovery rows when the parity definitions do not provide a sufficient number of independent linear equations to solve the unknown symbols of the failed nodes. The decoder can select recovery rows contiguous to the already identified recovery rows for access efficiency.

A system and method for memory error detection and recovery in a decoding system in CXL components is presented. The method includes receiving, into a first decoder within the decoding system, a memory transfer block (MTB) having data and parity information, and having a vertical portion and a horizontal portion, performing error detection and correction on the vertical portion of the MTB using binary hamming code logic within the first decoder; and upon performing error detection and correction in the first decoder, then forwarding MTB to a second decoder, and performing error detection and correction, via the second decoder, on the horizontal portion of the MTB using a non-binary hamming code logic within the second decoder such that the first and second decoders perform the error detection and correction on the vertical and horizontal portions of the MTB in a serial manner.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Cable systems and assemblies integrate a reduced number of twin axial cables to transmit and received in a full-duplex transmission signals at transmission speeds greater than or equal to one hundred Giga bytes per second. The reduced number of twin axial cables comprise four or less twin axial cables, in which each pair forms a single twin axial full-duplex cable for passive or active communication of the signals at multiple different transmission rates concurrently. A processor can be integrated with the twin axial cables and operate to encode the signals for fast transmission speeds at the different transmission rates.