Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

Provided herein is a conductive pattern making method and conductive pattern, the method including forming a groove such that its width in an inlet area is bigger than its width in an inner area; filling the groove with a conductive ink composition; and drying the conductive ink composition so that a solvent contained in the conductive ink composition inside the groove is volatilized to reduce the volume of the conductive ink composition.

Provided are an electronic component manufacturing method by which even a platable layer made of a difficult-to-plate material can be easily plated with good adhesion without using a special chemical solution or a photolithography technique, and an electronic component which has a peel strength of 0.1 N/mm or greater as measured by a copper foil peel test. A picosecond laser beam having a pulse duration on the order of a picosecond or a femtosecond laser beam having a pulse duration on the order of a femtosecond is emitted at a surface of a platable layer (2) in order to roughen the surface, a wiring pattern is formed using a mask (13), and a plated part (12) is formed on the surface of the wiring pattern.

A chip part includes a substrate, a first electrode and a second electrode which are formed apart from each other on the substrate and a circuit network which is formed between the first electrode and the second electrode. The circuit network includes a first passive element including a first conductive member embedded in a first trench formed in the substrate and a second passive element including a second conductive member formed on the substrate outside the first trench.

Provided is a double layer circuit board and a manufacturing method thereof. The double layer circuit board comprises a substrate, a first circuit layer formed on a first surface of the substrate, a second circuit layer formed on a second surface of the substrate, and at least one connecting pillar formed in and covered by the substrate. Each one of the at least one connecting pillar includes a first end connected to the first circuit layer and a second end connected to the second circuit layer. A terminal area of the second end is greater than a terminal area of the first end. Therefore, the second circuit layer is firmly connected to the first circuit layer through the at least one connecting pillar. A yield rate of the double layer circuit board may be increased.

A package structure includes a substrate, a sensor, a base, a lead frame, conductive vias and patterned circuit layer. The substrate includes a component-disposing region and electrode contacts. The sensor is disposed at the component-disposing region and electrically connected to the electrode contacts. The base covers the substrate with its bonding surface and includes a receiving cavity, a slanted surface extended between a bottom surface of the receiving cavity and the bonding surface, and electrodes disposed on the bonding surface and electrically connected to the electrode contacts respectively. The sensor is located in the receiving cavity. The lead frame is disposed at the base. The conductive vias penetrates the base and electrically connected to the lead frame. The patterned circuit layer is disposed on the slanted surface and electrically connected to the conductive vias and the electrodes.

A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Disclosed is a transparent electrode including a transparent substrate 100, conductive nanowires 10 forming networks, nanoparticles bonding the nanowires 10, and a conductive layer embedded in the transparent substrate 100.

A formation method of circuit board structure is disclosed. The formation method comprises: forming an intermediate substrate having interconnections therein and circuit patterns on both upper and lower surfaces, wherein the interconnections electrically connect the upper and lower circuit patterns; forming an upper dielectric layer overlying the upper circuit patterns, wherein the upper dielectric layer has a plurality of trenches therein; forming conductive wires in the trenches using e-less plating; and forming at least one protective layer overlying the conductive wires using a surface finishing process. The circuit board structure features formation of embedded conductive wires in the dielectric layer so that a short circuit can be avoid.

A component carrier for carrying electronic components, wherein the component carrier comprises an at least partially electrically insulating core, at least one electronic component embedded in the core, and a coupling structure with at least one electrically conductive through-connection extending at least partially therethrough and having a component contacting end and a wiring contacting end, wherein the at least one electronic component is electrically contacted directly to the component contacting end, wherein at least an exterior surface portion of the coupling structure has homogeneous ablation properties and is patterned so as to have surface recesses filled with an electrically conductive wiring structure, and wherein the wiring contacting end is electrically contacted directly to the wiring structure.