A method is provided for fabricating a semiconductor wafer having a device side, a back side opposite the device side and an outer periphery edge. Suitably, the method includes: forming a top conducting layer on the device side of the semiconductor wafer; forming a passivation layer over the top conducting layer, the passivation layer being formed so as not to extend to the outer periphery edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin coated over the passivation layer so as to have a smooth top surface at least in a region proximate to the outer periphery edge of the semiconductor wafer.

Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

A lithographic printing plate precursor including an image recording layer containing an infrared absorber represented by Formula I, on a support, and a method of producing a lithographic printing plate and a lithographic printing method using the lithographic printing plate precursor. ##STR00001##

There is provided resist underlayer film for lithography process with high dry etching resistance, wiggling resistance, and heat resistance. Resist underlayer film-forming composition for lithography including polymer having unit structure of Formula (1): wherein A is hydroxy group-substituted C.sub.6-40 arylene group derived from polyhydroxy aromatic compound; B is C.sub.6-40 arylene group or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof; X.sup.+ is H.sup.+, NH.sub.4.sup.+, primary ammonium ion, secondary ammonium ion, tertiary ammonium ion, or quaternary ammonium ion, T is hydrogen atom, C.sub.1-10 alkyl group or C.sub.6-40 aryl group that may be substituted with halogen group, hydroxy group, nitro group, amino group, carboxylate ester group, nitrile group, or combination thereof as substituent, or C.sub.4-30 heterocyclic group containing nitrogen atom, oxygen atom, sulfur atom, or combination thereof, B and T may form C.sub.4-40 ring together with carbon atom to which they are bonded. ##STR00001##

A method of manufacturing a patterned stamp (100) for patterning a contoured surface (10) is disclosed. The method comprises applying a layer (115) of a pliable material precursor over a master (50) carrying an inverse pattern (52) to form a desired pattern (112) in said layer; curing the pliable material precursor to form a pliable stamp layer (120) comprising said desired pattern; providing an intermediate stamp structure by adhering a porous pliable support layer (130) to the pliable stamp layer; releasing the intermediate stamp structure from the master; forcing the intermediate stamp structure onto the contoured surface with said pattern of features facing the contoured surface; forming the patterned stamp by filling the porous pliable support layer with a filler material to reduce the pliability of the support layer; and removing the patterned stamp from the contoured surface. A corresponding patterned stamp, imprinting method and imprinted article are also disclosed.

A photomask layout includes: a substrate region; a lower stepped region at a region of the substrate region; and a pattern region at least partially crossing the lower stepped region and including at least one notch portion at an area overlapping the lower stepped region. A method of forming a pattern is also provided.

Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Disclosed are methods of advanced process control (APC) for particular processes. A particular process (e.g., a photolithography or etch process) is performed on a wafer to create a pattern of features. A parameter is measured on a target feature and the value of the parameter is used for APC. However, instead of performing APC based directly on the actual parameter value, APC is performed based on an adjusted parameter value. Specifically, an offset amount (which is previously determined based on an average of a distribution of parameter values across all of the features) is applied to the actual parameter value to acquire an adjusted parameter value, which better represents the majority of features in the pattern. Performing this APC method minimizes dimension variations from pattern to pattern each time the same pattern is generated on another region of the same wafer or on a different wafer using the particular process.

A reticle enclosure includes a base including a first surface, a cover including a second surface and coupled to the base with the first surface facing the second surface. The base and the cover form an internal space that includes a reticle. The reticle enclosure includes restraining mechanisms arranged in the internal space and for securing the reticle, and structures disposed adjacent the reticle in the internal space. The structures enclose the reticle at least partially, and limit passage of contaminants between the internal space and an external environment of the reticle enclosure. The structures include barriers disposed on the first and second surfaces. In other examples, a padding is installed in gaps between the barriers and the first and second surfaces. In other examples, the structures include wall structures disposed on the first and second surfaces and between the restraining mechanisms.