A device (100) includes a light source (130) and a light guide (110). The light source (130) is configured to emit photoresist-curative electromagnetic radiation. The light guide (110) is arranged to receive the photoresist-curative electromagnetic radiation from the light source (130) and to guide the received radiation by total internal reflection, the light guide (110) including a pattern of emission points (210) on at least one surface of the light guide (110), the emission points (210) emitting the photoresist-curative electromagnetic radiation out of the light guide (110) by frustration of total internal reflection caused by the emission points (210).

A method of processing a substrate includes: providing structures on a surface of a substrate; depositing a self-assembled monolayer (SAM) over the structures and the substrate, the SAM being reactive to a predetermined wavelength of radiation; determining a first pattern of radiation exposure, the first pattern of radiation exposure having a spatially variable radiation intensity across the surface of the substrate and the structures; exposing the SAM to radiation according to the first pattern of radiation exposure, the SAM being configured to react with the radiation; developing the SAM with a predetermined removal fluid to remove portions of the SAM that are not protected from the predetermined fluid; and depositing a spacer material on the substrate and the structures, the spacer material being deposited at varying thicknesses based on an amount of the SAM remaining on the surface of the substrate and the structures.

Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit formed by two cross-coupled inverters, and a pass-gate transistor coupling an output of the latch circuit to a bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line through a first contact over the first source/drain region and a first via over the first contact. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line through a second contact over the second source/drain region and a second via over the second contact. Height of the second via is greater than height of the first via. The local interconnect line and the bit line are formed in the same metal layer. The bit line is thicker than the local interconnect line.

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

A method of forming a photoresist pattern and a semiconductor device on which a photoresist pattern manufactured according to the same is formed. The method includes forming a photoresist pattern on a substrate; coating an organic topcoat composition including an acrylic polymer including a structural unit containing a hydroxy group and a fluorine and an acidic compound on the photoresist pattern; drying and heating the substrate on which the organic topcoat composition is coated to coat it with a topcoat; and spraying a rinse solution including an ether-based compound on the substrate coated with the topcoat to remove the topcoat.

Novel photoresist additive compositions including developer solubility groups which enhance the solubility of the photoresist additive in a developer, such as a TMAH developer. The novel photoresist additive compositions also include functional groups to address outgassing and out-of-band issues.

Techniques described herein relate to methods, apparatus, and systems for promoting adhesion between a substrate and a metal-containing photoresist. For instance, the method may include receiving the substrate in a reaction chamber, the substrate having a first material exposed on its surface, the first material including a silicon-based material and/or a carbon-based material; generating a plasma from a plasma generation gas source that is substantially free of silicon, where the plasma includes chemical functional groups; exposing the substrate to the plasma to modify the surface of the substrate by forming bonds between the first material and chemical functional groups from the plasma; and depositing the metal-containing photoresist on the modified surface of the substrate, where the bonds between the first material and the chemical functional groups promote adhesion between the substrate and the metal-containing photoresist.

The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

Provided are photoresist compositions for EUV and methods for manufacturing a semiconductor device using the same. The photoresist compositions for EUV include a photosensitive resin, a photoacid generator, and an additive, wherein the additive comprises a copolymer including a first repeating unit that includes a fluoroalkyl group or hydrocarbon group substituted with one or more fluoroalkyl group(s), and a second repeating unit that includes a sulfonic acid group and an amide group.

A method includes transferring a wafer to a position over a wafer chuck; ejecting a first gas from a purging device above the wafer to clean a top surface of the wafer; after ejecting the first gas, lifting a lifting pin through the wafer chuck to receive the wafer; and after the wafer is received by the lifting pin, ejecting a second gas from first openings in a sidewall of the lifting pin to a region between a bottom surface of the wafer and a top surface of the wafer chuck.