Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

A method of method of operating a multibeamlet charged particle device is disclosed. In the method, a target attached to a stage is translated, and each step of selecting beamlets, initializing beamlets, and exposing the target is repeated. The step of selecting beamlets includes passing a reconfigurable plurality of selected beamlets through the blanking circuit. The step of initializing beamlets includes pointing each of the selected beamlets in an initial direction. The step of exposing the target includes scanning each of the selected beamlets from the initial direction to a final direction, and irradiating a plurality of regions of the target on the stage with the selected beamlets.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

A method of creating electronic devices such as semiconductor chips using a maskless lithographic exposure system such as a charged particle multi-beamlet lithography system (301A-301D). The maskless lithographic exposure system comprises a lithography subsystem (316) including a maskless pattern writer such as a charged particle multi-beamlet lithography machine (1) or ebeam machine. The method comprises introducing unique chip design data (430) or information related thereto into pattern data comprising common chip design data before streaming the pattern data to the maskless pattern writer.

Position shifts caused by charging phenomena can be corrected with high accuracy. A charged particle beam writing apparatus includes an exposure-amount distribution calculator calculating an exposure amount distribution of a charged particle beam using a pattern density distribution and a dose distribution, a fogging charged particle amount distribution calculator calculating a plurality of fogging charged particle amount distributions by convoluting each of a plurality of distribution functions for fogging charged particles with the exposure amount distribution, a charge-amount distribution calculator calculating a charge amount distribution due to direct charge using the pattern density distribution, the dose distribution, and the exposure amount distribution, and calculating a plurality of charge amount distributions due to fogging charge using the plurality of fogging charged particle amount distributions, a position shift amount calculator calculating a position shift amount of a writing position based on the charge amount distribution due to direct charge and the plurality of charge amount distributions due to fogging charge, a corrector correcting an exposure position using the position shift amount, and a writer exposing the corrected exposure position to a charged particle beam.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

Disclosed are systems and methods for achieving sub-diffraction limit resolutions for fabrication of integrated circuits using multiphoton lithography. In one embodiment, a photolithography system is disclosed. The system includes a light source, which can generate and emit laser beams at various wavelengths; a reflector configured to receive the laser beams and focus the laser beams on a condensing lens; a scattering medium, configured to receive the laser beams and generate scattered laser beams; and a wave-front shaping module, configured to receive the scattered laser beams and generate a focused laser beam in a photoresist material deposited on a silicon wafer.

According to one embodiment, an imprint lithography template comprises a substrate transparent to ultraviolet light. A first mesa region is on the substrate. A surface of the first mesa region includes a pattern region to be pressed into a photocurable resist film. The pattern region having four sides. A second mesa region is also on the substrate. The first mesa region protrudes from a surface of the second mesa region. A blocking film is adjacent to two sides of the four sides pattern region. The two sides to which the blocking film is adjacent are connected to each other at a corner of the pattern region. The blocking film blocks ultraviolet light.

A template includes: a base material having a surface including a first pattern, a second pattern and a third pattern, the first pattern including a first recess, the second pattern including a second recess. The base material containing a first material having a first refractive index; a first layer disposed in the first recess and containing a second material, the second material having a second refractive index different from the first refractive index; and a second layer disposed in the second recess, containing the second material, and being thicker than the first layer.

Methods for fabricating thin, high-aspect-ratio Ge nanostructures from high-quality, single-crystalline Ge substrates are provided. Also provided are grating structures made using the methods. The methods utilize a thin layer of graphene between a surface of a Ge substrate, and an overlying resist layer. The graphene passivates the surface, preventing the formation of water-soluble native Ge oxides that can result in the lift-off of the resist during the development of the resist.