A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

A method of method of operating a multibeamlet charged particle device is disclosed. In the method, a target attached to a stage is translated, and each step of selecting beamlets, initializing beamlets, and exposing the target is repeated. The step of selecting beamlets includes passing a reconfigurable plurality of selected beamlets through the blanking circuit. The step of initializing beamlets includes pointing each of the selected beamlets in an initial direction. The step of exposing the target includes scanning each of the selected beamlets from the initial direction to a final direction, and irradiating a plurality of regions of the target on the stage with the selected beamlets.

An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.

A method comprising contact-free positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a device pattern wafer. The template mask wafer includes a semitransparent layer. The method includes contact-free aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device pattern wafer and contacting the mask wafer on the device pattern wafer. The method includes transferring a template device pattern of the template mask wafer onto the predetermined surface area section of the device pattern wafer using an electron beam while heat conduction is distributed throughout the mask wafer to maintain a low temperature rise in the mask wafer during the transferring. A system is also provided.

A method comprising contact-free positioning a template mask wafer having a template device pattern relative to a predetermined surface area section of a device pattern wafer. The template mask wafer includes a semitransparent layer. The method includes contact-free aligning one or more mask alignment marks of the template mask wafer with one or more alignment marks of the device pattern wafer and contacting the mask wafer on the device pattern wafer. The method includes transferring a template device pattern of the template mask wafer onto the predetermined surface area section of the device pattern wafer using an electron beam while heat conduction is distributed throughout the mask wafer to maintain a low temperature rise in the mask wafer during the transferring. A system is also provided.

Methods for fabricating thin, high-aspect-ratio Ge nanostructures from high-quality, single-crystalline Ge substrates are provided. Also provided are grating structures made using the methods. The methods utilize a thin layer of graphene between a surface of a Ge substrate, and an overlying resist layer. The graphene passivates the surface, preventing the formation of water-soluble native Ge oxides that can result in the lift-off of the resist during the development of the resist.

Photoresist layers of semiconductor components including electric fields. The photoresist layer may include a body including a first portion disposed directly over a conductive layer of the semiconductor component. The body may also include a second portion integrally formed with and positioned over the first portion. The second portion may include a surface formed opposite the first portion. Additionally, the second portion may include a plurality of charged-particles implanted therein, where the plurality of charged-particles generating an electric field may extend through the first portion and the second portion of the body.

Disclosed are methods of forming a pattern and methods of fabricating a semiconductor device. A method of fabricating a semiconductor device may include providing a substrate comprising a resist layer on the substrate and coating a compound on the resist layer to form a charge dissipation layer. The charge dissipation layer may include a conductive polymer and a metal complex.

A resist underlayer film-forming composition exhibiting high etching resistance, high heat resistance, and excellent coatability; a resist underlayer film obtained using the resist underlayer film-forming composition and a method for producing the same; a method for forming a resist pattern; and a method for producing a semiconductor device. A resist underlayer film-forming composition including a polymer and a compound represented by Formula (1) as a solvent.

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In Formula (1), R.sup.1, R.sup.2, and R.sup.3 in Formula (1) each independently represent a hydrogen atom or an alkyl group having 1 to 20 carbon atoms, which may be interrupted by an oxygen atom, a sulfur atom, or an amide bond, and R.sup.1, R.sup.2, and R.sup.3 may be the same or different and may bond to each other to form a ring structure.

The conductive film of the present invention includes a conductive polymer (A) and has a film thickness of 35 nm or less, wherein: a surface resistance of the conductive film is 110.sup.11 /sq. or less, and a standard deviation of current that flows through the conductive film upon application of voltage to the conductive film is 5 or less. The conductor of the present invention has a substrate, and the conductive film provided on at least a part of the surface of the substrate. The resist pattern forming method of the present invention includes a lamination step of forming the conductive film on a surface of a resist layer including a chemically amplified resist, said resist layer formed on one surface of a substrate, and an exposure step of irradiating the substrate with an electron beam according to a pattern on its side on which the conductive film is formed. The laminate of the present invention has a resist layer and an antistatic film formed on the surface of the resist layer, wherein the antistatic film is the above-mentioned conductive film.