A method of making a semiconductor structure, the method including forming a conductive layer over a substrate. The method further includes forming a first imaging layer over the conductive layer, where the first imaging layer comprises a plurality of layers. The method further includes forming openings in the first imaging layer to expose a first set of areas of the conductive layer. The method further includes implanting ions into each area of the first set of area. The method further includes forming a second imaging layer over the conductive layer. The method further includes forming openings in the second imaging layer to expose a second set of areas of the conductive layer, wherein the second set of areas is different from the first set of areas. The method further includes implanting ions into the each area of the second set of areas.

Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

According to one embodiment, a pattern formation method includes forming a base structure including first and second guide portions each including a pinning portion, and a neutral portion, forming a block copolymer film containing first and second polymers on the bass structure, performing a predetermined treatment for the block copolymer film, thereby forming first and second pattern portions formed of the first polymer, forming third and fourth pattern portions formed of the second polymer, and forming a fifth pattern portion formed of the first and second polymers. The fifth pattern portion includes a plurality of first portions formed of the second polymer, and a second portion formed of the first polymer and provided on the neutral portion and the first portions.

The present disclosure provides a self-aligned two-time forming method capable of preventing sidewalls from being deformed, comprises sequentially growing a first silicon nitride layer, a first silicon oxide layer, a titanium nitride layer, a second silicon oxide layer, a second silicon nitride layer and a polysilicon layer on a via layer from bottom to top; defining a pattern by using the polysilicon layer as a hard mask, and etching the second silicon nitride layer to an upper surface of the second silicon oxide layer to form a plurality of silicon nitride pattern structures from the second silicon nitride layer; forming sidewalls on sidewalls of the plurality of silicon nitride pattern structures; removing the silicon nitride pattern structures in the sidewalls; etching the silicon nitride layer and the titanium nitride layer by using the sidewalls as a hard mask to form a titanium nitride pattern structure.

Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and performing a first etch on the mandrel layer, the first etch forming a first opening exposing a first portion of the substrate. The mandrel layer is masked with a second mask and a second etch is performed on the mandrel layer. The second etch forms a second opening exposing a second portion of the substrate, and also forms a protective layer on the first portion of the substrate and in the first opening.

Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has having a first group of openings defined therebetween and etching the spacer layer disposed on the substrate while forming an oxidation layer on the spacer layer.

A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions in a first direction. Each first region adjoins adjacent second regions, and each second region includes a trench region. The method includes forming a first mask layer on the to-be-etched layer; implanting doping ions into the first mask layer outside of the trench region; forming a doped separation layer in the first mask layer of the second region to divide the first mask layer into portions arranged in a second direction perpendicular to the first direction; forming a first trench in the first mask layer of the first region; and removing the first mask layer formed in the trench region on both sides of the doped separation layer to form a second trench divided into portions arranged in the second direction by the doped separation layer.

A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.

A resist underlayer film-forming composition including: (A) component: an isopoly or heteropoly acid, or a salt thereof, or a combination thereof; and (B) component: polysiloxan, poly hafnium oxide or zirconium oxide, or a combination thereof, wherein an amount of the (A) component is 0.1 to 85% by mass of a total amount of the (A) component and the (B) component; and polysiloxan is a hydrolysis-condensation product of hydrolyzable silane of Formula (1):
R.sup.1.sub.aR.sup.2.sub.bSi(R.sup.3).sub.4−(a+b)  Formula (1)
and a hydrolyzable silane whose (a+b) is 0 is contained in a proportion of 60 to 85 mol % of a total hydrolyzable silane in Formula (1); the poly hafnium oxide is a hydrolysis-condensation product of hydrolyzable hafnium of Formula (2):
Hf(R.sup.4).sub.4  Formula (2)
and the zirconium oxide is a hydrolysis-condensation product of hydrolyzable zirconium of Formula (3) or Formula (4):
Zr(R.sup.5).sub.4  Formula (3)
ZrO(R.sup.6).sub.2  Formula (4)
or a hydrolysis-condensation product of a combination thereof.