Atomic layer deposition (ALD) processes for forming Group VA element containing thin films, such as Sb, Sb—Te, Ge—Sb and Ge—Sb—Te thin films are provided, along with related compositions and structures. Sb precursors of the formula Sb(SiR.sup.1R.sup.2R.sup.3).sub.3 are preferably used, wherein R.sup.1, R.sup.2, and R.sup.3 are alkyl groups. As, Bi and P precursors are also described. Methods are also provided for synthesizing these Sb precursors. Methods are also provided for using the Sb thin films in phase change memory devices.

Described herein are methods for improved transfer of graphene from formation substrates to target substrates. In particular, the methods described herein are useful in the transfer of high-quality chemical vapor deposition-grown monolayers of graphene from metal, e.g., copper, formation substrates to ultrathin, flexible glass targets. The improved processes provide graphene materials with less defects in the structure.

A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.

A method is provided for fabricating a semiconductor structure. The method includes forming a base substrate including a substrate and a stress layer formed in the substrate, where a top surface of the stress layer is higher than a surface of the substrate. The method also includes forming a first cover layer, where a first growth rate difference exists between growth rates of the first cover layer on the top surface of the stress layer and the first cover layer on a side surface of the stress layer. Further, the method includes forming a second cover layer, where a second growth rate difference exists between growth rates of the second cover layer on the top surface of the stress layer and the second cover layer on the side surface of the stress layer, and the second growth rate difference is larger than the first growth rate difference.

A semiconductor device wafer includes a plurality of device patterns formed in or over a semiconductor substrate, and a scribe area from which the device patterns are excluded. A plurality of dummy features are located in at least one material level in the scribe area, including over laser scribe dots formed in the semiconductor substrate.

An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Various implementations of a method of forming a semiconductor package may include forming a plurality of notches into the first side of a semiconductor substrate; applying a permanent coating material into the plurality of notches; forming a first organic material over the first side of the semiconductor substrate and the plurality of notches; thinning a second side of the semiconductor substrate opposite the first side one of to or into the plurality of notches; and singulating the semiconductor substrate through the permanent coating material into a plurality of semiconductor packages.

Implementations of a semiconductor device may include a semiconductor die including a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof where the semiconductor die may be coupled with one of a substrate, a leadframe, an interposer, a package, a bonding surface, or a mounting surface. The thickness may be between 0.1 microns and 125 microns.