A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.

A method for forming a FET device is provided, the method including: forming a fin structure; while masking the fin structure from a second side of the fin structure opposite a first side of the fin structure: etching each of first and second fin parts laterally from the first side such that a set of source cavities and a set of drain cavities is formed in first non-channel layers in the first fin part and the second fin part, and subsequently, forming a source body and a drain body, each comprising a respective common body portion along the first side and a set of prongs protruding from the respective common body portion into the source and drain cavities, respectively, and abutting the channel layers; and while masking the fin structure from the first side: etching the third fin part laterally from the second side such that a set of gate cavities extending through the third fin part is formed in second non-channel layers, and subsequently, forming a gate body comprising a common gate body portion along the second side and a set of gate prongs protruding from the common gate body portion into the gate cavities.

A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

A vapor deposition apparatus includes an exhaust regulator provided in an exhaust pipe to regulate exhaust of the reaction chamber and including: a hollow frustum upstream baffle having a larger first opening near a reaction chamber than a second opening near an exhaust device; and a hollow frustum downstream baffle provided near the exhaust device with respect to the upstream baffle and having a larger third opening near the reaction chamber than a fourth opening near the exhaust device. The upstream baffle and downstream baffle are designed so that B/A and C/A are 0.33 or less, at least one of B/A and C/A is 0.26 or less, and (B+C)/A is 0.59 or less, where an inner diameter of the exhaust pipe and diameters of the first and third openings are A, a diameter of the second opening is B and a diameter of the fourth opening is C.

Improved methods for chemically etching silicon are provided herein. In some embodiments, a method of etching a silicon material includes: (a) exposing the silicon material to a halogen-containing gas; (b) evacuating the halogen-containing gas from the semiconductor processing chamber; (c) exposing the silicon material to an amine vapor to etch a monolayer of the silicon material; (d) evacuating the amine vapor from the semiconductor processing chamber and; (e) optionally repeating (a)-(d) to etch the silicon material to a predetermined thickness.

Improved methods for chemically etching silicon are provided herein. In some embodiments, a method of etching a silicon material includes: (a) exposing the silicon material to a halogen-containing gas; (b) evacuating the halogen-containing gas from the semiconductor processing chamber; (c) exposing the silicon material to an amine vapor to etch a monolayer of the silicon material; (d) evacuating the amine vapor from the semiconductor processing chamber and; (e) optionally repeating (a)-(d) to etch the silicon material to a predetermined thickness.

In some embodiments, the present disclosure relates to a high-resistivity silicon-on-insulator (SOI) substrate, including a first polysilicon layer arranged over a semiconductor substrate. A second polysilicon layer is arranged over the first polysilicon layer, and a third polysilicon layer is arranged over the second polysilicon layer. An active semiconductor layer over an insulator layer may be arranged over the third polysilicon layer. The second polysilicon layer has an elevated concentration of oxygen compared to the first and third polysilicon layers.

A SiC wafer is processed by a laser beam having a wavelength that transmits SiC to form a peeling plane in a region of the wafer which corresponds to a device area of a first surface of the wafer. A plurality of devices demarcated by a plurality of intersecting projected dicing lines in the device area are formed on the first surface. An annular groove is formed on a second surface of the wafer which is opposite the first surface, in a boundary region of the wafer between the device area and an outer peripheral excessive area surrounding the device area. A portion of the wafer which is positioned radially inwardly of the annular groove is peeled from the peeling plane, thereby thinning the device area and forming an annular stiffener area on a region of the second surface which corresponds to the outer peripheral excessive area.

A SiC wafer is processed by a laser beam having a wavelength that transmits SiC to form a peeling plane in a region of the wafer which corresponds to a device area of a first surface of the wafer. A plurality of devices demarcated by a plurality of intersecting projected dicing lines in the device area are formed on the first surface. An annular groove is formed on a second surface of the wafer which is opposite the first surface, in a boundary region of the wafer between the device area and an outer peripheral excessive area surrounding the device area. A portion of the wafer which is positioned radially inwardly of the annular groove is peeled from the peeling plane, thereby thinning the device area and forming an annular stiffener area on a region of the second surface which corresponds to the outer peripheral excessive area.

A method of manufacturing a semiconductor device includes irradiating the semiconductor body with particles through a first side of the semiconductor body, removing at least a part of impurities from an irradiated part of the semiconductor body by out-diffusion during thermal treatment in a temperature range between 450° C. to 1200° C., and forming a first load terminal structure at the first side of the semiconductor body.