Disclosed embodiments apply electron beams to substrates for microelectronic workpieces to improve plasma etch and deposition processes. The electron beams are generated and directed to substrate surfaces using DC (direct current) biasing, RF (radio frequency) plasma sources, and/or other electron beam generation and control techniques. For certain embodiments, DC-biased RF plasma sources, such as DC superposition (DCS) or hybrid DC-RF sources, are used to provide controllable electron beams on surfaces opposite a DC-biased electrode. For certain further embodiments, the DC-biased electrode is pulsed. Further, electron beams can also be generated through electron beam extraction from external and/or non-ambipolar sources. The disclosed techniques can also be used with additional electron beam sources and/or additional etch or deposition processes.

A method is provided for the processing of a device having a crystalline silicon region containing an internal hydrogen source. The method comprises: i) applying encapsulating material to each of the front and rear surfaces of the device to form a lamination; ii) applying pressure to the lamination and heating the lamination to bond the encapsulating material to the device; and iii) cooling the device, where the heating step or cooling step or both are completed under illumination.

A silicon fin precursor is formed in an nFET device region and a fin stack comprising alternating material portions, and from bottom to top, of silicon and a silicon germanium alloy is formed in a pFET device region. A thermal anneal is then used to convert the fin stack into a silicon germanium alloy fin precursor. A thermal oxidation process follows that converts the silicon fin precursor into a silicon fin and the silicon germanium alloy fin precursor into a silicon germanium alloy fin. Functional gate structures can be formed straddling over each of the various fins.

A method of producing silicon single crystal ingot by pulling the silicon single crystal ingot made of an N-region by the CZ method, including: performing an EOSF inspection including a heat treatment to manifest oxide precipitates and selective etching on sample wafer from the silicon single crystal ingot composed of the N-region to measure a density of EOSF; performing a shallow-pit inspection to investigate a pattern of occurrence of a shallow pit; adjusting the pulling conditions according to result of identification of a defect region of the sample wafer by the EOSF and shallow-pit inspections to pull a next silicon single crystal ingot composed of the N-region, wherein in the identification of the defect region, for an N-region, what portion of an Nv-region or Ni-region the defect region corresponds to is also identified.

A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having a gettering layer formed inside the wafer. The method includes the steps of applying excitation light for exciting a carrier to the wafer, applying microwaves to a light applied area where the excitation light is applied and also to an area other than the light applied area, measuring the intensity of the microwaves reflected from the light applied area and from the area other than the light applied area, subtracting the intensity of the microwaves reflected from the area other than the light applied area from the intensity of the microwaves reflected from the light applied area to thereby obtain a differential signal, and determining the gettering property of the gettering layer according to the intensity of the differential signal obtained above.

An RF SOI switch includes patterned or self-aligned low-k features (i.e., low-k polymer structures or voids) in the PMD and/or subsequently formed inter-metal dielectric layers to reduce capacitive coupling. All portions of the dielectric layers through which metal contact/via structures pass are pre-designated as reserved regions, and formation of the low-k features is restricted to interstitial regions located between adjacent reserved regions. After the low-k features are formed, dielectric material is deposited into all reserved regions, and then the metal contact/via structures are formed according to standard practices through the dielectric material disposed in the reserved regions. The low-k features are formed by polymer material sandwiched between two passivation layers. Optional openings are formed through the upper passivation layer, and then the polymer material is asked out to generate void-type features. Optionally, polymer is spin-coated over the metal line structures, then etched back to form self-aligned low-k features.

A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.

The present invention provides a method for evaluating a semiconductor substrate subjected to a defect recovery heat treatment to recover a crystal defect in the semiconductor substrate having the crystal defect, flash lamp annealing is performed as the defect recovery heat treatment, and the method includes steps of measuring the crystal defect in the semiconductor substrate, which is being recovered, by controlling treatment conditions for the flash lamp annealing and analyzing a recovery mechanism of the crystal defect on the basis of a result of the measurement. Consequently, the method for evaluating a semiconductor substrate which enables evaluating a recovery process of the crystal defect is provided.

After determining the size of oxygen precipitates and the residual oxygen concentration in a silicon wafer after heat treatment performed in a device fabrication process; the critical shear stress τ.sub.cri at which slip dislocations are formed in the silicon wafer in the device fabrication process is determined based on the obtained size of the oxygen precipitates and residual oxygen concentration; and the obtained critical shear stress τ.sub.cri and the thermal stress τ applied to the silicon wafer in the heat treatment of the device fabrication process are compared, thereby determining that slip dislocations are formed in the silicon wafer in the device fabrication process when the thermal stress τ is equal to or more than the critical shear stress τ.sub.cri, or determining that slip dislocations are not formed in the silicon wafer in the device fabrication process when the thermal stress τ is less than the critical shear stress τ.sub.cri.