Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

The present invention relates to a method for preparing a SiC—Si.sub.3N.sub.4 composite material and a SiC—Si.sub.3N.sub.4 composite material prepared according to same and comprises the steps of: preparing a mold; and forming a SiC—Si.sub.3N.sub.4 composite material by introducing, to the mold, a source gas comprising Si, N and C, at 1100 to 1600° C. More particularly, the present invention provides the SiC—Si.sub.3N.sub.4 composite material of high purity that is applicable to a semiconductor process, and increases the thermal shock strength of a SiC material by causing Si.sub.3N.sub.4, which is a material with a high thermal shock strength, to grow together via a CVD method.

A method of manufacturing nitride semiconductor substrate, comprising: providing silicon-on-insulator substrate which comprises an underlying silicon layer, a buried silicon dioxide layer and a top silicon layer; forming a first nitride semiconductor layer on the top silicon layer; forming, in the first nitride semiconductor layer, a plurality of notches which expose the top silicon layer; removing the top silicon layer and forming a plurality of protrusions and a plurality of recesses on an upper surface of the buried silicon dioxide layer, wherein each of the plurality of protrusions is in contact with the first nitride semiconductor layer, and there is a gap between each of the plurality of recesses and the first nitride semiconductor layer; and epitaxially growing a second nitride semiconductor layer on the first nitride semiconductor layer, such that the first nitride semiconductor layer and the second nitride semiconductor layer form a nitride semiconductor substrate.

The disclosure provides a control device of an annealing device, which is capable of further suppressing a temperature of a surface opposite to a laser irradiation surface from rising. A beam spot of a pulsed laser beam output from a laser light source on a surface of an annealed target is shaped into a long shape in one direction by a beam shaping optical element. A movement mechanism moves the beam spot with respect to the annealed target. The control device controls the laser light source and the movement mechanism and performs annealing by performing a sweep operation of moving the beam spot in a longitudinal direction of the beam spot with respect to the annealed target while causing the pulsed laser beam to be incident on the annealed target.

The disclosure provides a control device of an annealing device, which is capable of further suppressing a temperature of a surface opposite to a laser irradiation surface from rising. A beam spot of a pulsed laser beam output from a laser light source on a surface of an annealed target is shaped into a long shape in one direction by a beam shaping optical element. A movement mechanism moves the beam spot with respect to the annealed target. The control device controls the laser light source and the movement mechanism and performs annealing by performing a sweep operation of moving the beam spot in a longitudinal direction of the beam spot with respect to the annealed target while causing the pulsed laser beam to be incident on the annealed target.

A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.

In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom substrate disk includes a first heating mechanism. The heatable bottom substrate disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom substrate disk. A heatable top substrate disk comprising a second heating mechanism. The heatable top substrate disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom substrate disk. While the heatable top substrate disk applies the mechanical pressure a chamber pressure is maintained at a specified low value. The first heating mechanism and the second heating mechanism can be independently tuned to any value in the working range.

In one aspect, a highly scalable diffusion-couple apparatus includes a transfer chamber configured to load a wafer into a process chamber. The process chamber is configured to receive the wafer substrate from the transfer chamber. The process chamber comprises a chamber for growth of a diffusion material on the wafer. A heatable bottom substrate disk includes a first heating mechanism. The heatable bottom substrate disk is fixed and heatable to a specified temperature. The wafer is placed on the heatable bottom substrate disk. A heatable top substrate disk comprising a second heating mechanism. The heatable top substrate disk is configured to move up and down along an x axis and an x prime axis to apply a mechanical pressure to the wafer on the heatable bottom substrate disk. While the heatable top substrate disk applies the mechanical pressure a chamber pressure is maintained at a specified low value. The first heating mechanism and the second heating mechanism can be independently tuned to any value in the working range.