A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound.

A semiconductor package includes a carrier, at least and adhesive portion, a plurality of micro pins and a die. The carrier has a first surface and second surface opposite to the first surface. The adhesive portion is disposed on the first surface, and the plurality of the micro pins is disposed in the adhesive portions. The die is disposed on the remaining adhesive portion free of the micro pins.

A method of manufacturing a semiconductor device may include forming an adhesive film on a surface of a semiconductor chip, mounting the semiconductor chip on a substrate such that the adhesive film contacts an upper surface of the substrate, and bonding the semiconductor chip and the substrate curing the adhesive film by simultaneously performing a thermo-compression process and an ultraviolet irradiation process on the adhesive film disposed between the substrate and the semiconductor chip.

Electronic devices including a layer of polymeric material and solid semiconductor dies partially embedded in the layer are provided. The dies have first ends projecting away from the first major surface of the layer. The electronic devices can be formed by sinking the first ends of the dies into a major surface of a liner. A flowable polymeric material is filled into the space between the dies and solidified to form the layer of polymeric material. The first ends of the dies are exposed by delaminating the liner from the first ends of the dies. Electrical conductors are provided on the layer to connect the first ends of the dies.

A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

A method for manufacturing a photoelectric conversion device, that includes: forming a laminate structure of a substrate, a transparent electrode, an active layer produced by wet-coating, and a counter electrode, stacked in this order; and thereafter forming a cavity by: (a) pressing an adhesive material just against a defect formed on the surface of said counter electrode, and then peeling off said adhesive material together with said defect and the peripheral part thereof; or (b) sucking a defect formed on the surface of said counter electrode, so as to remove said defect and the peripheral part thereof, where said cavity penetrates through the counter electrode and unreached to the transparent electrode.

A cover for an integrated circuit package includes a central plate and a peripheral frame surrounding the central plate. The peripheral frame is vertically spaced from and parallel to the central plate. The peripheral frame includes through openings formed therein. The cover can be used to package a semiconductor chip that is mounted to a substrate.

Provided is a semiconductor device formed by performing bonding at room temperature with respect to a wafer in which bonded electrodes and insulating layers and are respectively exposed to front surfaces, including a bonding interlayer which independently exhibits non-conductivity and exhibits conductivity by being bonded to the bonded electrodes, between the front surfaces.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a bottom side, a bottom coating located on the bottom side and an electrode layer located on an underside of the bottom coating facing away from the semiconductor layer sequence, wherein the bottom coating has a thickness gradient and at least one ridge line at which the bottom coating is thickest, wherein the electrode layer extends over the at least one ridge line such that a contact side of the electrode layer facing away from the semiconductor layer sequence follows the bottom coating true to shape, and wherein an electrical and mechanical contact plane of the contact side parallel to the bottom side is defined by the at least one ridge line.

In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.