A nitride semiconductor device is provided that includes: a substrate; an n-type drift layer above the front surface of the substrate; a p-type base layer above the n-type drift layer; a gate opening in the base layer that reaches the drift layer; an n-type channel forming layer that covers the gate opening and has a channel region; a gate electrode above a section of the channel forming layer in the gate opening; an opening that is separated from the gate electrode and reaches the base layer; an opening formed in a bottom surface of said opening and reaching the drift layer; a source electrode covering the openings; and a drain electrode on the rear surface of the substrate.

A nitride semiconductor device is provided that includes: a substrate; an n-type drift layer above the front surface of the substrate; a p-type base layer above the n-type drift layer; a gate opening in the base layer that reaches the drift layer; an n-type channel forming layer that covers the gate opening and has a channel region; a gate electrode above a section of the channel forming layer in the gate opening; an opening that is separated from the gate electrode and reaches the base layer; an opening formed in a bottom surface of said opening and reaching the drift layer; a source electrode covering the openings; and a drain electrode on the rear surface of the substrate.

Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel; and a die pad on which at least one of the PN junction diodes and the Schottky barrier diode are mounted commonly.

Provided is a semiconductor device including, a plurality of PN junction diodes each having a negative temperature characteristic and connected to each other in series; a plurality of resistance elements connected respectively to the PN junction diodes in parallel and connected to each other in series; and a Schottky barrier diode having a positive temperature characteristic and connected to the PN junction diodes in parallel.

There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.

There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.

A semiconductor device includes a control circuit configured to suppress a current variation by turning on or off a constant current source when transitioning to a standby mode. The control circuit has a function of predicting a current variation value from register information and information of current profile. The control circuit has a function of optimizing single control amount of the current source and the number of times of control of the current source based on the predicted current variation value.

In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

Integrated circuit equipped with at least two levels of superimposed transistors, comprising: a first transistor at a first level, a first plug, a second plug and a third plug, connected to a drain region, a gate and a source region respectively of the first transistor, the first plug, the second plug and the third plug passing through an insulating layer covering the first transistor a second transistor equipped with an active zone defined in a semi-conducting layer arranged at one end of the plugs and facing the first transistor, the transistor comprising a gate arranged between the first plug and the third plug.

Disclosed herein is a composite transistor which includes a first transistor TR.sub.1 including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor TR.sub.2 including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.