Three-dimensional non-volatile memory structure and manufacturing method thereof

Abstract

A three-dimensional non-volatile memory structure including a substrate, a stacked structure, a charge storage pillar, a channel pillar, and a ferroelectric material pillar is provided. The stacked structure is disposed on the substrate and includes a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked. The charge storage pillar is disposed in the stacked structure. The channel pillar is disposed inside the charge storage pillar. The ferroelectric material pillar is disposed inside the channel pillar.

Claims

1. A three-dimensional non-volatile memory structure, comprising: a substrate; a stacked structure disposed on the substrate and comprising a plurality of conductive layers and a plurality of first dielectric layers, wherein the conductive layers and the first dielectric layers are alternately stacked; a charge storage pillar disposed in the stacked structure; a channel pillar disposed inside the charge storage pillar; and a ferroelectric material pillar disposed inside the channel pillar.

2. The three-dimensional non-volatile memory structure of claim 1, wherein a material of the conductive layers comprises a metal or a doped polysilicon, the metal comprises tungsten, a material of the first dielectric layers comprises silicon oxide, and a material of the channel pillar comprises polysilicon.

3. The three-dimensional non-volatile memory structure of claim 1, wherein the charge storage pillar comprises: a second dielectric layer adjoined to the stacked structure; a third dielectric layer adjoined to the channel pillar; and a charge trapping layer located between the second dielectric layer and the third dielectric layer.

4. The three-dimensional non-volatile memory structure of claim 3, wherein a material of the second dielectric layer and the third dielectric layer comprises silicon oxide, and a material of the charge trapping layer comprises silicon nitride.

5. The three-dimensional non-volatile memory structure of claim 1, wherein the ferroelectric material pillar has ferroelectric negative capacitance characteristics.

6. The three-dimensional non-volatile memory structure of claim 1, wherein a material of the ferroelectric material pillar comprises HfZrO, HfAlO, HfSiO, HfYO, HfLaO, HfGdO, HfSrO, HfSmO, PZT, BST, SBT, PLZT, LiNbO.sub.3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, SrAlF.sub.5, PVDF, PVDF-TrEE, or La.sub.1-xSr.sub.xMnO.sub.3.

7. The three-dimensional non-volatile memory structure of claim 6, wherein a doping ratio of Zr of HfZrO is 30% to 70%, a doping ratio of Al of HfAlO is 2% to 12%, a doping ratio of Si of HfSiO is 2% to 5%, a doping ratio of Y of HfYO is 2% to 12%, a doping ratio of La of HfLaO is 3% to 6%, a doping ratio of Gd of HfGdO is 2% to 6%, a doping ratio of Sr of HfSrO is 2% to 6%, a doping ratio of Sm of HfSmO is 2% to 6%.

8. The three-dimensional non-volatile memory structure of claim 1, further comprising a conductive pillar disposed inside the ferroelectric material pillar.

9. The three-dimensional non-volatile memory structure of claim 8, wherein a material of the conductive pillar comprises a metal compound.

10. The three-dimensional non-volatile memory structure of claim 9, wherein the metal compound comprises metal nitride or metal carbide.

11. The three-dimensional non-volatile memory structure of claim 10, wherein the metal compound comprises titanium nitride, tantalum nitride, tantalum carbon nitride, tungsten nitride, titanium tungsten nitride, titanium carbide, titanium aluminum carbide, tantalum carbide, tantalum aluminum carbide, or niobium aluminum carbide.

12. A manufacturing method of a three-dimensional non-volatile memory structure, comprising: forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of conductive layers and a plurality of first dielectric layers, and the conductive layers and the first dielectric layers are alternately stacked; forming a charge storage pillar in the stacked structure; forming a channel pillar inside the charge storage pillar; and forming a ferroelectric material pillar inside the channel pillar.

13. The manufacturing method of the three-dimensional non-volatile memory structure of claim 12, wherein the charge storage pillar comprises: a second dielectric layer adjoined to the stacked structure; a third dielectric layer adjoined to the channel pillar, and a charge trapping layer located between the second dielectric layer and the third dielectric layer.

14. The manufacturing method of the three-dimensional non-volatile memory structure of claim 12, wherein the ferroelectric material pillar has ferroelectric negative capacitance characteristics.

15. The manufacturing method of the three-dimensional non-volatile memory structure of claim 12, wherein a material of the ferroelectric material pillar comprises HtZrO, HfAlO, HfSiO, HfYO, HfLaO, HfGdO, HfSrO, HfSmO, PZT, BST, SBT, PLZT, LiNbO.sub.3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, SrAlF.sub.5, PVDF, PVDF-TrEE, or La.sub.1-xSr.sub.xMnO.sub.3.

16. The manufacturing method of the three-dimensional non-volatile memory structure of claim 15, wherein a doping ratio of Zr of HfZrO is 30% to 70%, a doping ratio of Al of HfAlO is 2% to 12%, a doping ratio of Si of HfSiO is 2% to 5%, a doping ratio of Y of HfYO is 2% to 12%, a doping ratio of La of HfLaO is 3% to 6%, a doping ratio of Gd of HfGdO is 2% to 6%, a doping ratio of Sr of HfSrO is 2% to 6%, a doping ratio of Sm of HfSmO is 2% to 6%.

17. The manufacturing method of the three-dimensional non-volatile memory structure of claim 12, further comprising forming a conductive pillar inside the ferroelectric material pillar.

18. The manufacturing method of the three-dimensional non-volatile memory structure of claim 17, wherein a material of the conductive pillar comprises a metal compound.

19. The manufacturing method of the three-dimensional non-volatile memory structure of claim 18, wherein the metal compound comprises metal nitride or metal carbide.

20. The manufacturing method of the three-dimensional non-volatile memory structure of claim 19, wherein the metal compound comprises titanium nitride, tantalum nitride, tantalum carbon nitride, tungsten nitride, titanium tungsten nitride, titanium carbide, titanium aluminum carbide, tantalum carbide, tantalum aluminum carbide, or niobium aluminum carbide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

(2) FIG. 1A is a three-dimensional schematic diagram of a three-dimensional non-volatile memory structure of an embodiment of the invention.

(3) FIG. 1B is a partial three-dimensional schematic diagram of FIG. 1A.

(4) FIG. 1C is a cross-section along section line I-I′ in FIG. 1A.

(5) FIG. 2A is a three-dimensional schematic diagram of a three-dimensional non-volatile memory structure of an embodiment of the invention.

(6) FIG. 2B is a partial three-dimensional schematic diagram of FIG. 2A.

(7) FIG. 2C is a cross-section along section line II-II′ in FIG. 2A.

(8) FIG. 3 is a flow chart of manufacturing a three-dimensional non-volatile memory structure of an embodiment of the invention.

(9) FIG. 4 is an I.sub.D (drain current)-V.sub.G (gate voltage) curve of the hafnium zirconium oxide memory device of the experimental example of the invention and a known memory device.

(10) FIG. 5 shows the relationship of polarization characteristics and electric field of hafnium oxide (HfO.sub.2) and hafnium zirconium oxide (HfZrO).

(11) FIG. 6 shows atomic structures of monoclinic phase and orthorhombic phase hafnium oxide.

(12) FIG. 7 is a grazing incident X-ray diffraction (GI-XRD) diagram of a ferroelectric material-hafnium zirconium oxide film.

(13) FIG. 8 is an I.sub.D-V.sub.G curve of the hafnium zirconium oxide memory device of the experimental example of the invention.

(14) FIG. 9 is a diagram of the relationship of polarization characteristics versus energy and dU/dP of the hafnium zirconium oxide memory device of the experimental example of the invention.

(15) FIG. 10 is a curve diagram showing a result of an endurance test of the hafnium zirconium oxide memory device of the experimental example of the invention.

(16) FIG. 11 is a curve diagram showing the ferroelectric-antiferroelectric phase conversion speed of the hafnium zirconium oxide memory device of the experimental example of the invention.

(17) FIG. 12 is an electric field distribution of a memory device adopting different internal oxides.

(18) FIG. 13 is an I.sub.D-V.sub.G curve of a memory device adopting different internal oxides during a programming operation.

(19) FIG. 14 is an I.sub.D-V.sub.G curve of a memory device adopting different internal oxides during an erase operation.

DESCRIPTION OF THE EMBODIMENTS

(20) Embodiments of the present invention may comprise any one or more of the novel features described herein, including in the Detailed Description, and/or shown in the drawings. As used herein, “at least one”, “one or more”, and “and/or” are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions “at least on of A, B and C”, “at least one of A, B, or C”, “one or more of A, B, and C”, “one or more of A, B, or C” and “A, B, and/or C” means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B and C together.

(21) It is to be noted that the term “a” or “an” entity refers to one or more of that entity. As such, the terms “a” (or “an”), “one or more” and “at least one” can be used interchangeably herein.

(22) FIG. 1A is a three-dimensional schematic diagram of a three-dimensional non-volatile memory structure of an embodiment of the invention. FIG. 1B is a partial three-dimensional schematic diagram of FIG. 1A describing the relative locations of the components. FIG. 1C is a cross-section along section line I-I′ in FIG. 1A.

(23) Referring to all of FIG. 1A to FIG. 1C, a three-dimensional non-volatile memory structure 100 includes a substrate 101, a stacked structure 102, a charge storage pillar 104, a channel pillar 106, and a ferroelectric material pillar 108. In the present embodiment, the three-dimensional non-volatile memory structure 100 is exemplified by a three-dimensional NAND flash memory, but the invention is not limited thereto. The substrate 101 is, for instance, a semiconductor substrate such as a silicon substrate.

(24) The stacked structure 102 is disposed on the substrate 101 and includes a plurality of conductive layers 110 and a plurality of dielectric layers 112 that are alternately stacked. The stacked structure 102 has an opening 114, and the opening 114 can expose the substrate 101. The conductive layer 110 can be used as a control gate, and the material thereof is, for instance, metal or doped polysilicon, wherein the metal is, for instance, tungsten. The dielectric layer 112 can be used as a blocking layer, and the material thereof is, for instance, silicon oxide.

(25) The charge storage pillar 104 is disposed in the stacked structure 102, such as disposed in the opening 114 of the stacked structure 102. The charge storage pillar 104 includes a dielectric layer 116, a dielectric layer 120, and a charge trapping layer 118. In particular, the dielectric layer 116 is adjoined to the stacked structure 102 and can be used as a blocking layer, and the material thereof is, for instance, silicon oxide. The dielectric layer 120 is adjoined to the channel pillar 106, the dielectric layer 120 can be used as a tunneling dielectric layer, and the material thereof is, for instance, silicon oxide. The charge trapping layer 118 is located between the dielectric layer 116 and the dielectric layer 120, and the material of the charge trapping layer 118 is, for instance, silicon nitride.

(26) The channel pillar 106 is disposed inside the charge storage pillar 104 and adjoined to the dielectric layer 120, the material of the channel pillar 106 is, for instance, polysilicon. The channel pillar 106 can be used as the vertical channel of the three-dimensional non-volatile memory structure 100.

(27) The ferroelectric material pillar 108 is disposed inside the channel pillar 106 and adjoined to the channel pillar 106. Since the ferroelectric material can restrict the crystal size in the material of the channel pillar 106, leakage current can be effectively reduced. Moreover, since the ferroelectric material has a high dielectric constant (high k value), electric field distribution can be changed, and as a result, the operating voltage of the memory can be reduced and the operating speed can be increased, and instability of threshold voltage drift can be improved. Accordingly, the three-dimensional non-volatile memory structure 100 can have better electrical performance.

(28) The ferroelectric material pillar 108 can have ferroelectric negative capacitance characteristics, and in addition to further reducing the operating voltage and power consumption caused by switching and increasing conduction current and reducing subthreshold swing of the memory device, the Off-state leakage current (I.sub.off) of the memory device can be further reduced.

(29) The material of the ferroelectric material pillar 108 is, for instance, hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO), hafnium yttrium oxide (HfYO), hafnium lanthanum oxide (HfLaO), hafnium gadolinium oxide (HfGdO), hafnium strontium oxide (HfSrO), hafnium samarium oxide (HfSmO), lead zirconate titanate (PZT), barium strontium titanate (BST), strontium bismuth tantalate (SBT), lead lanthanum zirconate titanate (PLZT), LiNbO.sub.3, BaMgF, BaMnF, BaFeF, BaCoF, BaNiF, BaZnF, SrAlF.sub.5, polyvinylidene difluoride (PVDF), PVDF-trifluoroethlene (PVDF-TrEE), or La.sub.1-xSr.sub.xMnO.sub.3. The forming method of the ferroelectric material pillar 108 is, for instance, a chemical vapor deposition method or a physical vapor deposition method.

(30) If the ferroelectric material pillar 108 is a ferroelectric material for which hafnium oxide is the base material, a doping process can be performed using a dopant such as Zr, Al, Si, Y, La, Gd, Sr, or Sm. For instance, the doping ratio of Zr of HfZrO can be 30% to 70%. The doping ratio of Al of HfAlO can be 2% to 12%. The doping ratio of Si of HfSiO can be 2% to 5%. The doping ratio of Y of HfYO can be 2% to 12%. The doping ratio of La of HfLaO can be 3% to 6%. The doping ratio of Gd of HfGdO can be 2% to 6%. The doping ratio of Sr of HfSrO can be 2% to 6%. The doping ratio of Sm of HfSmO can be 2% to 6%.

(31) Moreover, the three-dimensional non-volatile memory structure 100 can further include a doped region (not shown) located in the substrate 101 and a wire (not shown) located above the channel pillar 106 respectively used as the source line and the bit line.

(32) It can be known from the above embodiments that, since the ferroelectric material pillar 108 is disposed inside the channel pillar 106, leakage current can be effectively reduced, the operating voltage of the memory can be reduced and the operating speed can be increased, and instability of threshold voltage drift can be improved. As a result, the three-dimensional non-volatile memory structure 100 can have better electrical performance.

(33) FIG. 2A is a three-dimensional schematic diagram of a three-dimensional non-volatile memory structure of an embodiment of the invention. FIG. 2B is a partial three-dimensional schematic diagram of FIG. 2A describing the relative locations of the components. FIG. 2B is a cross-section along section line II-II′ in FIG. 2A.

(34) Referring to all of FIG. 1A to FIG. 1C and FIG. 2A to FIG. 2C, the differences between a three-dimensional non-volatile memory structure 200 and the three-dimensional non-volatile memory structure 100 are: the three-dimensional non-volatile memory structure 200 further includes a conductive pillar 122, and the conductive pillar 122 is disposed inside the ferroelectric material pillar 108 and can be a single-layer structure or a multi-layer structure, and the material thereof is, for instance, a material that can provide greater stress, such as a metal compound. The metal compound is, for instance, metal nitride or metal carbide such as titanium nitride (TiN), tantalum nitride (TaN), tantalum carbon nitride (TaCN), tungsten nitride (WN), titanium tungsten nitride (TiWN), titanium carbide (TiC), titanium aluminum carbide (TiAIC), tantalum carbide (TaC), tantalum aluminum carbide (TaAlC), or niobium aluminum carbide (NbAlC). The forming method of the conductive pillar 122 is, for instance, a chemical vapor deposition method or a physical vapor deposition method. Moreover, other similar members in the three-dimensional non-volatile memory structure 200 and the three-dimensional non-volatile memory structure 100 are represented by the same reference numerals and descriptions thereof are omitted.

(35) It can be known from the above embodiments that, in the three-dimensional non-volatile memory structure 200, since the conductive pillar 122 can be used as an inner gate, the control capability for the memory device can be effectively increased. Moreover, when the ferroelectric material pillar 108 is subjected to the strain effect caused by the conductive pillar 122, the material of the ferroelectric material pillar 108 is more readily phase-transformed from metastable state monoclinic phase to orthorhombic phase to improve ferroelectric characteristics and ferroelectric negative capacitance characteristics. As a result, the operating speed and endurance of the memory device can be further increased.

(36) FIG. 3 is a flow chart of manufacturing a three-dimensional non-volatile memory structure of an embodiment of the invention.

(37) Hereinafter, the manufacturing methods of the three-dimensional non-volatile memory structure 100 and the three-dimensional non-volatile memory structure 200 of the above embodiments are described via FIG. 3, but the invention is not limited thereto.

(38) Referring to FIGS. 1A-IC and FIG. 3, the manufacturing method of the three-dimensional non-volatile memory structure 100 can include step S100 to step S106. Step S100 is performed to form a stacked structure 102 on a substrate 101, wherein the stacked structure 102 includes a plurality of conductive layers 110 and a plurality of dielectric layers 112 that are alternately stacked. Step S102 is performed to form a charge storage pillar 104 in the stacked structure 102. The charge storage pillar 104 includes a dielectric layer 116, a dielectric layer 120, and a charge trapping layer 118, wherein the dielectric layer 116 is adjoined to the stacked structure 102, the dielectric layer 120 is adjoined to a channel pillar 106, and the charge trapping layer 118 is located between the dielectric layer 116 and the dielectric layer 120. Step S104 is performed to form the channel pillar 106 inside the charge storage pillar 104. Step S106 is performed to form a ferroelectric material pillar 108 inside the channel pillar 106.

(39) Referring to FIGS. 2A-2B and FIG. 3, the manufacturing method of the three-dimensional non-volatile memory structure 200 not only includes step S100 to step S106, but also includes step S108 to form a conductive pillar 122 inside the ferroelectric material pillar 108.

(40) Hereinafter, the electrical performance of the three-dimensional non-volatile memory structures of the above embodiments is described via an experimental example, but the following experimental example is only exemplary, and the invention is not limited thereto.

(41) FIG. 4 is an I.sub.D-V.sub.G curve of the hafnium zirconium oxide memory device of the experimental example of the invention and a known memory device.

(42) Referring to FIG. 4, in comparison to the subthreshold swing (SS) curve of a traditional memory device limited to an SS of 60 mV/dec, since the memory device of the experimental example of the invention adopts a ferroelectric material having ferroelectric negative capacitance characteristics, the memory device of the experimental example of the invention can generate a steeper SS curve via a ferroelectric negative-capacitance effect, such that not only can reduce the operating voltage (V.sub.DO) and the power consumption caused by switching of the memory device, the Off-state leakage current (I.sub.off) of the memory device can also be lowered.

(43) FIG. 5 shows the relationship of polarization characteristics and electric field of hafnium oxide (HfO.sub.2) and hafnium zirconium oxide (HfZrO).

(44) Referring to FIG. 5, the dotted line is the hysteresis curve of ferroelectric material-hafnium zirconium oxide (HfZrO), the solid line is the hysteresis curve of hafnium oxide (HfO.sub.2), and the auxiliary line L is a virtual and unstable hysteresis curve simulated according to a Landau model. Since dP/dE of the auxiliary line L is less than 0, the ferroelectric material-hafnium zirconium oxide is proven to have ferroelectric negative capacitance characteristics.

(45) FIG. 6 shows atomic structures of monoclinic phase and orthorhombic phase hafnium oxide.

(46) Referring to FIG. 6, the crystal phase of hafnium oxide can be transformed from metastable monoclinic phase to the more stable orthorhombic phase only when hafnium oxide (HfO.sub.2) is subjected to a greater strain so as to achieve ferroelectric negative capacitance characteristics.

(47) FIG. 7 is a grazing incident X-ray diffraction (GI-XRD) diagram of a ferroelectric material-hafnium zirconium oxide film.

(48) Referring to FIG. 7, by measuring the ferroelectric material-hafnium zirconium oxide (HfZrO) film via a grazing incident X-ray diffraction (GI-XRD) method, it can be known that the crystal phase of the ferroelectric material-hafnium zirconium oxide (HfZrO) film is orthorhombic phase.

(49) FIG. 8 is an I.sub.D-V.sub.G curve of the hafnium zirconium oxide memory device of the experimental example of the invention.

(50) Referring to FIG. 8, a sweep is performed on the hafnium zirconium oxide memory device of the experimental example of the invention at biases of +6V and −6V, and the drain voltage (V.sub.D) is −0.2 V. It can be known from the I.sub.D-V.sub.G curve of FIG. 8 that, the ferroelectric material can reduce the subthreshold swing (SS) and have ferroelectric negative capacitance characteristics. In comparison to the SS curve of a traditional memory device limited to an SS of 60 mV/dec, since the memory device of the experimental example of the invention adopts a ferroelectric material having ferroelectric negative capacitance characteristics, the SS can be less than 60 mV/dec, for example, as low as 58 mV/dec and 59 mV/dec.

(51) FIG. 9 is a diagram of the relationship of polarization characteristics versus energy and dU/dP of the hafnium zirconium oxide memory device of the experimental example of the invention.

(52) Referring to FIG. 9, the curve formed by the white squares shows the relationship of polarization characteristics and energy, and the curve formed by the black rhombi is the dU/dP curve obtained after differentiation. It is clear from FIG. 9 that, the dU/dP curve has two regions of local negative slope (dotted boxes in FIG. 9). In a negative capacitance model, this indicates that a ferroelectric negative capacitance effect is present in a bi-stable potential well in the memory device of the experimental example of the invention.

(53) FIG. 10 is a curve diagram showing a result of an endurance test of the hafnium zirconium oxide memory device of the experimental example of the invention.

(54) Referring to FIG. 10, during the programming and erase operations under the operating conditions of voltages of +5 V and −5 V and a pulse of 20 ns, the memory device of the experimental example of the invention can still be measured to have stable ΔV.sub.T (threshold voltage difference) even after 10.sup.12 programming/erasing (P/E) cycles at 25° C. Therefore, the memory device of the experimental example of the invention has better endurance and memory characteristics.

(55) FIG. 11 is a curve diagram showing the ferroelectric-antiferroelectric phase conversion speed of the hafnium zirconium oxide memory device of the experimental example of the invention.

(56) Referring to FIG. 11, a rapid current response discloses the ferroelectric-antiferroelectric (FE-AFE) phase transition time in a programming state is only 10 ns. Therefore, the operating speed of the memory device of the experimental example of the invention is fast.

(57) FIG. 12 is an electric field distribution of a memory device adopting different internal oxides.

(58) Referring to FIG. 12, in comparison to a memory device adopting silicon dioxide (SiO.sub.2) and hafnium oxide (HfO.sub.2) as the internal oxides, since the memory device of the experimental example of the invention adopts ferroelectric material-hafnium zirconium oxide as the internal oxide, it can be observed that the electric field is higher at the location of the internal oxide, and therefore better electric field control capability is achieved.

(59) FIG. 13 is an I.sub.D-V.sub.G curve of a memory device adopting different internal oxides during a programming operation. FIG. 14 is an I.sub.D-V.sub.G curve of a memory device adopting different internal oxides during an erase operation.

(60) Referring to FIG. 13 and FIG. 14, when programming operation and erase operation are performed at a drain voltage (V.sub.D) of 0.1 V, in comparison to a memory device adopting silicon dioxide (SiO.sub.2) and hafnium oxide (HfO.sub.2) as the internal oxides, since the memory device of the experimental example of the invention adopts ferroelectric material-hafnium zirconium oxide as the internal oxide, a greater ON-state current is achieved. Moreover, since the memory device of the experimental example of the invention adopts ferroelectric material-hafnium zirconium oxide as the internal oxide, a smaller threshold voltage (V.sub.T) is achieved. It can therefore be proven that, the memory device of the experimental example of the invention can have lower operating voltage, and therefore operating speed can be increased.

(61) Based on the above, in the three-dimensional non-volatile memory structure and the manufacturing method thereof of the above embodiments, since the ferroelectric material pillar is disposed inside the channel pillar, leakage current can be effectively reduced, the operating voltage of the memory can be reduced and the operating speed can be increased, and instability of threshold voltage drift can be improved. As a result, the three-dimensional non-volatile memory structure can have better electrical performance.

(62) The previously described exemplary embodiments of the present invention have many advantages, including effectively reducing leakage current, reducing the operating voltage of the memory, increasing the operating speed, improving instability of threshold voltage drift and having better electrical performance, wherein the advantages aforementioned not required in all versions of the invention.

(63) Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention is defined by the attached claims not by the above detailed descriptions.