A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

Various techniques and apparatus permit fabrication of superconductive circuits. A superconducting integrated circuit comprising a superconducting stud via, a kinetic inductor, and a capacitor may be formed. Forming a superconducting stud via in a superconducting integrated circuit may include masking with a hard mask and masking with a soft mask. Forming a superconducting stud via in a superconducting integrated circuit may include depositing a dielectric etch stop layer. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by an electrical vernier. Interlayer misalignment in the fabrication of a superconducting integrated circuit may be measured by a chain of electrical verniers and a Wheatstone bridge. A superconducting integrated circuit with three or more metal layers may include an enclosed, matched, on-chip transmission line. A metal wiring layer in a superconducting integrated circuit may be encapsulated.

A superconducting circuit includes a first component having a first connection point. The first connection point has a first width. The superconducting circuit includes a second component having a second connection point. The second connection point has a second width that is larger than the first width. The superconducting circuit includes a superconducting connector shaped to reduce current crowding. The superconducting connector electrically connects the first connection point and the second connection point. The superconducting connector includes a first taper positioned adjacent the first connection point and having a non-linear shape and a second taper positioned adjacent the second connection point.

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

A quantum bit device according to the present invention includes a first quantum bit substrate 10 which includes a first superconductive wiring 13 disposed to have a magnetically coupled portion with a first superconductive magnetic flux quantum bit 14 on a surface thereof, a second quantum bit substrate 11 which includes a second superconductive wiring 13 disposed to have a magnetically coupled portion with a second superconductive magnetic flux quantum bit 14 on a surface thereof, and a base substrate 12 which includes a third superconductive wiring 13 configured by two superconductive wirings extending parallel to each other on a surface thereof. The first and second quantum bit substrates are placed on the base substrate, two end portions of the first superconductive wiring and two end portions on one side of the third superconductive wiring are joined via superconductive solders 15, two end portions of the second superconductive wiring and two end portions on the other side of the third superconductive wiring are joined via superconductive solders 15, and three of the first to third superconductive wirings form one continuous superconductive loop.

A method of forming a composite crystalline nitride structure is provided. The method includes depositing a first crystalline nitride layer on a substrate, patterning the first crystalline nitride layer to form a patterned crystalline nitride layer having a top surface and that includes undulations, annealing the patterned crystalline nitride layer at a temperature between 300° C. to 850° C. to form an annealed patterned crystalline nitride layer, and depositing a second crystalline nitride layer on the annealed patterned crystalline nitride layer. The second crystalline nitride layer is lattice-matched to the underlying annealed patterned crystalline nitride layer to within 2%, thereby forming the composite crystalline nitride structure.

Disclosed are a silicon wafer and a method for filling a silicon via thereof, and belong to the field of superconducting quantum technologies. The method includes: obtaining a silicon wafer including at least one silicon via; providing a superconducting material on at least one side of the silicon wafer, the at least one side comprising a side where an opening of the silicon via is located; and heating and pressurizing the superconducting material to fill the superconducting material into the silicon via.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

A method of forming a superconducting structure is provided that includes forming a superconducting element in a first dielectric layer, forming a protective pad formed from a resistive material over at least a portion of the superconducting element, forming a second dielectric layer overlying the first dielectric layer, and etching an opening through the second dielectric layer to the protective pad, such that no portion of the superconducting element is exposed in the opening. A cleaning process is performed on the superconducting structure, and a contact material fill with a resistive material is performed to fill the opening and form a resistive element in contact with the superconducting element through the protective pad.

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.