A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

On a first superconducting layer deposited on a first surface of a substrate, a first component of a resonator is pattered. On a second superconducting layer deposited on a second surface of the substrate, a second component of the resonator is patterned. The first surface and the second surface are disposed relative to each other in a non-co-planar disposition. In the substrate, a recess is created, the recess extending from the first superconducting layer to the second superconducting layer. On an inner surface of the recess, a third superconducting layer is deposited, the third superconducting layer forming a superconducting path between the first superconducting layer and the second superconducting layer. Excess material of the third superconducting layer is removed from the first surface and the second surface, forming a completed through-silicon via (TSV).

A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.

A method of forming a superconductor interconnect structure is disclosed. The method includes forming a dielectric layer overlying a substrate, forming an interconnect opening in the dielectric layer, and moving the substrate to a deposition chamber. The method further includes depositing a superconducting metal in the interconnect opening, by performing a series of superconducting deposition and cooling processes to maintain a chamber temperature at or below a predetermined temperature until the superconducting metal has a desired thickness, to form a superconducting element in the superconductor interconnect structure.

Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.

A semiconductor structure and methods of forming the semiconductor structure generally includes providing a thermocompression bonded superconducting metal layer sandwiched between a first silicon substrate and a second silicon substrate. The second substrate includes a plurality of through silicon vias to the thermocompression bonded superconducting metal layer. A second superconducting metal is electroplated into the through silicon vias using the thermocompression bonded superconducting metal layer as a bottom electrode during the electroplating process, wherein the filling is from the bottom upwards.

An integrated circuit (IC) device includes a substrate having a fin-type active region extending in a first direction, a gate structure intersecting the fin-type active region on the substrate, the gate structure extending in a second direction perpendicular to the first direction and parallel to a top surface of the substrate, source and drain regions on both sides of the gate structure, and a first contact structure electrically connected to one of the source and drain regions, the first contact structure including a first contact plug including a first material and a first wetting layer surrounding the first contact plug, the first wetting layer including a second material having a lattice constant that differs from a lattice constant of the first material by about 10% or less.

Methods and structures corresponding to superconducting apparatus including superconducting layers and traces are provided. A method for forming a superconducting apparatus includes forming a first dielectric layer on a substrate by depositing a first dielectric material on the substrate and curing the first dielectric material at a first temperature. The method further includes forming a first superconducting layer comprising a first set of patterned superconducting traces on the first dielectric layer. The method further includes forming a second dielectric layer on the first superconducting layer by depositing a second dielectric material on the first superconducting layer and curing the second dielectric material at a second temperature, where the second temperature is lower than the first temperature. The method further includes forming a second superconducting layer comprising a second set of patterned superconducting traces on the second dielectric layer.

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

A low-noise wide band amplifier is realized utilizing a superconductor-insulator-superconductor (SIS) junction, quasiparticle frequency mixers connected in tandem or in cascade, a first quasiparticle mixer performs first frequency mixing with use of a first local signal having a frequency not less than twice a frequency of an input signal to the first quasiparticle mixer, a second quasiparticle mixer performs second frequency mixing with use of a second local signal having a frequency not more than twice a frequency of an input signal to the second quasiparticle mixer, and signal amplification is performed through frequency conversion by extracting, from among a plurality of signals generated with the first and the second frequency mixing, a signal in a frequency band not more than a frequency band of the signal before the first frequency mixing and the second frequency mixing, using a transmission line or a filter.